Method of making a low power SRAM

Claim 1

A method of making a static random access memory (SRAM) having a plurality of SRAM cells comprising pull down transistors and pass transistors, the method of making the SRAM comprising: providing a pull-down transistor by providing a gate electrode over a gate oxide layer, performing a first phosphorus implantation self aligned to the gate electrode, providing insulating spacers alongside the gate electrode, and performing a second phosphorus implantation self aligned to the insulating spacers, thereby providing a phosphorus LDD structure for a source and a drain of the pull down transistor, the source region connected to a low reference potential and the drain region connected to a charge storage node; masking the pull down transistor with an implantation mask to expose a portion of the pull down transistor that will be part of the source region of the pull down transistor and covering at least another portion of the pull down transistor that will be part of the drain region of the pull down transistor and implanting arsenic ions into the source region of the pull down transistor; providing a pass transistor connected between the charge storage node and a bit line; and providing a load device connected between the charge storage node and a high reference potential contact.

Claim 2

A method of making a static random access memory (SRAM) having a plurality of SRAM cells comprising pull down transistors and pass transistors, the method of making the SRAM comprising: providing a pull-down transistor by providing a gate electrode over a gate oxide layer, performing a first phosphorus implantation self aligned to the gate electrode, providing insulating spacers alongside the gate electrode, and performing a second phosphorus implantation self aligned to the insulating spacers, thereby providing a phosphorus LDD structure for a source and a drain of the pull down transistor, the source region connected to a low reference potential and the drain region connected to a charge storage node; masking the pull down transistor with an implantation mask to expose a portion of the pull down transistor that will be part of the source region of the pull down transistor and covering at least another portion of the pull down transistor that will be part of the drain region of the pull down transistor and implanting arsenic ions into the source region of the pull down transistor; providing a pass transistor connected between the charge storage node and a bit line; and providing a load device connected between the charge storage node and a high reference potential contact.

Claim 6

A method of making a static random access memory (SRAM) having a plurality of SRAM cells comprising pull down transistors and pass transistors, the method of making the SRAM comprising the steps of: providing a gate electrode over a gate oxide layer; performing a first phosphorus implantation self aligned to the gate electrode; providing insulating spacers alongside the gate electrode; performing a second phosphorus implantation self aligned to the insulating spacers, thereby to complete a phosphorus LDD structure for a source and a drain; connecting the source region to a low reference potential; connecting the drain region to a charge storage node; masking at least the drain region with an implantation mask while exposing the source region; implanting arsenic ions into the exposed source region while the drain region is masked, thereby to obtain a pull down transistor having a source doped with arsenic and a drain essentially free of arsenic; providing a pass transistor connected between the charge storage node and a bit line; and providing a load device connected between the charge storage node and a high reference potential contact.

Claim 7

A method of making a static random access memory (SRAM) having a plurality of SRAM cells comprising pull down transistors and pass transistors, the method of making the SRAM comprising the steps of: providing a gate electrode over a gate oxide layer; performing a first phosphorus implantation self aligned to the gate electrode; providing insulating spacers alongside the gate electrode; performing a second phosphorus implantation self aligned to the insulating spacers, thereby to complete a phosphorus LDD structure for a source and a drain; connecting the source region to a low reference potential; connecting the drain region to a charge storage node; masking at least the drain region with an implantation mask while exposing the source region; implanting arsenic ions into the exposed source region while the drain region is masked, thereby to obtain a pull down transistor having a source doped with arsenic and a drain essentially free of arsenic; providing a pass transistor connected between the charge storage node and a bit line; and providing a load device connected between the charge storage node and a high reference potential contact.

Claim 8

A method of making a static random access memory (SRAM) having a plurality of SRAM cells and an array of bit lines for addressing the SRAM cells, the method of making the SRAM comprising: providing for an SRAM cell a high reference potential contact, a lower reference potential contact, and a charge storage node; providing a pull-down transistor connected between the charge storage node and the lower reference potential contact, the pull-down transistor having a source connected to the lower reference potential and a drain connected to the charge storage node, wherein the pull-down transistor is formed by: providing a gate electrode over a gate oxide layer, performing a first phosphorus implantation self aligned to the gate electrode, providing insulating spacers alongside the gate electrode, performing a second phosphorus implantation self aligned to the insulating spacers, thereby providing a phosphorus LDD structure for the source and the drain of the pull-down transistor, masking the pull-down transistor with an implantation mask to expose a portion of the pull-down transistor that will be part of the source region of the pull-down transistor and covering at least another portion of the pull-down transistor that will be part of the drain region of the pull-down transistor, and implanting arsenic ions into the source region of the pull-down transistor, wherein the drain of the pull-down transistor does not include arsenic as a dopant; providing a pass transistor connected between the charge storage node and a bit line; and providing a load device connected between the charge storage node and the high reference potential contact.

Claim 9

A method of making a static random access memory (SRAM) having a plurality of SRAM cells and an array of bit lines for addressing the SRAM cells, the method of making the SRAM comprising: providing for an SRAM cell a high reference potential contact, a lower reference potential contact, and a charge storage node; providing a pull-down transistor connected between the charge storage node and the lower reference potential contact, the pull-down transistor having a source connected to the lower reference potential and a drain connected to the charge storage node, wherein the pull-down transistor is formed by: providing a gate electrode over a gate oxide layer, performing a first phosphorus implantation self aligned to the gate electrode, providing insulating spacers alongside the gate electrode, performing a second phosphorus implantation self aligned to the insulating spacers, thereby providing a phosphorus LDD structure for the source and the drain of the pull-down transistor, masking the pull-down transistor with an implantation mask to expose a portion of the pull-down transistor that will be part of the source region of the pull-down transistor and covering at least another portion of the pull-down transistor that will be part of the drain region of the pull-down transistor, and implanting arsenic ions into the source region of the pull-down transistor, wherein the drain of the pull-down transistor does not include arsenic as a dopant; providing a pass transistor connected between the charge storage node and a bit line; and providing a load device connected between the charge storage node and the high reference potential contact.

Claim 12

A method of making a static random access memory (SRAM) having a plurality of SRAM cells comprising pull-down transistors and pass transistors, the method of making the SRAM comprising: providing a pull-down transistor having a source and a drain, the drain of the pull-down transistor provided with a dopant consisting essentially of phosphorus, the source of the pull-down transistor having a higher dopant concentration than the drain of the pull-down transistor; masking the pull-down transistor with an implantation mask to expose a portion of the pull-down transistor that will be part of the source region of the pull-down transistor and covering at least another portion of the pull-down transistor that will be part of the drain region of the pull-down transistor and implanting arsenic ions into the source region of the pull-down transistor; providing a pass transistor connected between a charge storage node and a bit line; and providing a load device connected to the charge storage node and a reference potential contact.

Claim 13

A method of making a static random access memory (SRAM) having a plurality of SRAM cells comprising pull-down transistors and pass transistors, the method of making the SRAM comprising: providing a pull-down transistor having a source and a drain, the drain of the pull-down transistor provided with a dopant consisting essentially of phosphorus, the source of the pull-down transistor having a higher dopant concentration than the drain of the pull-down transistor; masking the pull-down transistor with an implantation mask to expose a portion of the pull-down transistor that will be part of the source region of the pull-down transistor and covering at least another portion of the pull-down transistor that will be part of the drain region of the pull-down transistor and implanting arsenic ions into the source region of the pull-down transistor; providing a pass transistor connected between a charge storage node and a bit line; and providing a load device connected to the charge storage node and a reference potential contact.