US5744839A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ESD protection using selective siliciding techniques
Assignee: Round Rock Research LLC
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Filing: 1996-06-11
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Granted: 1998-04-28
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Expires: 2016-06-11
Abstract
Abstract The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined discharge paths are created for discharging input and output buffer pads, during an ESD event, through ESD protection devices. During fabrication, an oxide layer is utilized as a mask to prevent silicided regions from forming in source/drain regions, self-aligned with the gates. The buffer transistor gate-to-contact spacing is made longer than the gate-to-contact spacing in the associated protection transistor, to shunt charge through the protection device. In a further embodiment, active area resistance is formed between the output/input buffer transistor and the ESD protection device, to further increase the resistance of the path between the buffer pad to the associated buffer transistor.
Inventors
- 👤 Manny K. F. Ma
- 👤 Aaron Schoenfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:42
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
68 words
An integrated circuit on a single semiconductor die, comprising: at least one buffer transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are not self-aligned with the gate; and, an ESD protection device having a silicided gate and silicided source/drain regions not self aligned with the gate and placed at a shorter length from the gate than such regions in the buffer transistor.
Claim 2
Dependent Claim
68 words
An integrated circuit on a single semiconductor die, comprising: at least one buffer transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are not self-aligned with the gate; and, an ESD protection device having a silicided gate and silicided source/drain regions not self aligned with the gate and placed at a shorter length from the gate than such regions in the buffer transistor.
Claim 3
Dependent Claim
50 words
The integrated circuit of claim 1, wherein the ratio of the length between the buffer transistor gate and the buffer transistor silicided source/drain region to the length between the ESD protection device gate and the ESD protection device silicided source/drain region is selected to provide protection from selected ESD events.
Claim 4
Dependent Claim
19 words
The integrated circuit of claim 1, wherein the ESD protection device is connected in parallel with the buffer transistor.
Claim 5
Dependent Claim
42 words
The integrated circuit of claim 3, wherein the buffer transistor is an output buffer transistor, and wherein the integrated circuit further comprises active area resistance coupled between the drain of the output buffer transistor and the drain of the ESD protection device.
Claim 6
Dependent Claim
12 words
The integrated circuit of claim 4, wherein the silicide comprises titanium silicide.
Claim 7
Dependent Claim
23 words
The integrated circuit of claim 5, wherein contacts are formed over the silicided areas of the drain in electrical contact with the drain.
Claim 8
Dependent Claim
42 words
The integrated circuit of claim 1, wherein the buffer transistor is an output buffer transistor, and wherein the integrated circuit further comprises active area resistance coupled between the drain of the output buffer transistor and the drain of the ESD protection device.
Claim 9
Dependent Claim
85 words
An integrated circuit on a single semiconductor die, comprising: a first transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are spaced greater than spacing normally provided by spacers formed on the sides of a gate; and, a second transistor coupled to the first transistor and having a silicided gate and silicided source/drain regions which are spaced from said silicided gate a shorter length from the gate than such regions are spaced from the silicided gate in the first transistor.
Claim 10
Dependent Claim
85 words
An integrated circuit on a single semiconductor die, comprising: a first transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are spaced greater than spacing normally provided by spacers formed on the sides of a gate; and, a second transistor coupled to the first transistor and having a silicided gate and silicided source/drain regions which are spaced from said silicided gate a shorter length from the gate than such regions are spaced from the silicided gate in the first transistor.
Claim 11
Dependent Claim
101 words
An integrated circuit on a single semiconductor die, comprising: a buffer transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are spaced greater than spacing normally provided by spacers formed on the sides of a gate; and, an ESD protection transistor coupled to the buffer transistor and having a silicided gate and silicided source/drain regions which are spaced from said silicided gate a shorter length from the gate than such regions are spaced from the silicided gate in the first transistor, wherein the ESD protection transistor turns on before the buffer transistor during an ESD event.
Claim 12
Dependent Claim
101 words
An integrated circuit on a single semiconductor die, comprising: a buffer transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are spaced greater than spacing normally provided by spacers formed on the sides of a gate; and, an ESD protection transistor coupled to the buffer transistor and having a silicided gate and silicided source/drain regions which are spaced from said silicided gate a shorter length from the gate than such regions are spaced from the silicided gate in the first transistor, wherein the ESD protection transistor turns on before the buffer transistor during an ESD event.
Claim 13
Dependent Claim
124 words
An integrated circuit on a single semiconductor die, comprising: a buffer transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are spaced by an oxide layer greater than spacing normally provided by spacers formed on the sides of a gate; an ESD protection transistor having a silicided gate and silicided source/drain regions which are spaced from said silicided gate by an oxide layer a shorter length from the gate than such regions are spaced from the silicided gate in the first transistor, wherein the ESD protection transistor turns on before the buffer transistor during an ESD event; and an active area resistor coupled between the drain of the output buffer transistor and the drain of the ESD protection transistor.
Claim 14
Dependent Claim
124 words
An integrated circuit on a single semiconductor die, comprising: a buffer transistor, having a silicided gate and silicided source/drain regions, wherein the silicided source/drain regions are spaced by an oxide layer greater than spacing normally provided by spacers formed on the sides of a gate; an ESD protection transistor having a silicided gate and silicided source/drain regions which are spaced from said silicided gate by an oxide layer a shorter length from the gate than such regions are spaced from the silicided gate in the first transistor, wherein the ESD protection transistor turns on before the buffer transistor during an ESD event; and an active area resistor coupled between the drain of the output buffer transistor and the drain of the ESD protection transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-04-27 | 2001-10-27 | 2002-04-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-04-27 | 2005-10-27 | 2006-04-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-04-27 | 2009-10-27 | 2010-04-28 | $7700.00 | Window Closed / Lapsed |