Process for fabrication of an SRAM cell having a highly doped storage node

Claim 1

A process for fabrication of an SRAM cell comprising a) formation of a gate oxide layer on a semiconductor substrate, b) formation of a gate layer on said gate oxide layer, c) formation of a first mask, d) etching said gate layer through said mask to form gate structure from said gate layer and exposing areas adjacent to said gate structure, e) performing a first ion implantation into said substrate in all exposed areas adjacent to said gate structure, f) then forming a second mask for a second ion implantation, g) performing a second ion implantation step through said second mask at least one exposed area adjacent to said gate structure, h) removing said second mask, i) deposition of a dielectric layer over said gate structure, j) etching said dielectric layer to form a spacer structure therefrom, with the remainder of said dielectric layer being removed by said etching, and k) performing a third ion implantation into said substrate in all regions exposed adjacent to said gate structure and said spacer structure forming more highly doped regions.