Method for fabricating a MOSFET device, for an SRAM cell, using a self-aligned ion implanted halo region

Claim 1

A method of fabricating a MOSFET device, for a SRAM cell, on a semiconductor substrate, using a self-aligned, halo, (SAC halo), implant region, in said MOSFET device, comprising the steps of: forming field oxide regions in said semiconductor substrate; growing a gate insulator layer on said semiconductor substrate, in areas not covered by said field oxide regions; depositing a first polysilicon layer on said gate insulator layer; depositing a first metal silicide layer on said first polysilicon layer; depositing a first insulator layer on said first metal silicide layer; patterning of said first insulator layer, of said first metal silicide layer, and of said first polysilicon layer, to form polycide gate structures, on said gate insulator layer; ion implanting a first conductivity imparting dopant into said semiconductor substrate, in regions not covered by said polycide gate structures, to form a lightly doped source and drain region; depositing a second insulator layer; anisotropic etching of said second insulator layer to form insulator spacers on the sides of said polycide gate structures; ion implanting a second conductivity imparting dopant into said semiconductor substrate, in regions not covered by said polycide gate structures, or not covered by said insulator spacers, to form a heavily doped source and drain region; depositing a third insulator layer; opening a hole in said third insulator layer, creating a self-aligned contact, (SAC), opening, exposing said heavily doped source and drain region, in said semiconductor substrate, in the space between said polycide gate structures, with said insulator spacers; ion implanting a third conductivity imparting dopant into said SAC opening, to create said SAC halo implant region, in said semiconductor substrate, in space between said polycide structures; depositing a second polysilicon layer, including deposition on said heavily doped source and drain region, and on said SAC halo implant region, in said SAC opening, in space between said polycide gate structures; depositing a second metal silicide layer on said second polysilicon layer; patterning of said second metal silicide layer, and of said second polysilicon layer, to create a polycide, self- aligned contact, (SAC), structure, completely overlying said SAC opening, and with said polycide SAC structure partially overlying a portion of said polysilicon gate structures, in regions where said polycide gate structures are adjacent to said SAC opening; depositing a fourth insulator layer; depositing a third polysilicon layer; patterning of said third polysilicon layer to create polysilicon load resistors; depositing a composite interlevel dielectric layer on said semiconductor substrate, including deposition on said polycide SAC structure, and on said polysilicon load resistors; annealing of said composite interlevel dielectric layer; opening contact holes in said composite interlevel dielectric layer, and in said fourth insulator layer, to expose top surface of said polycide SAC structure, and top surface of said polysilicon load resistors; and forming an interconnect metallization structures, overlying and contacting, said polycide SAC structure, and said polysilicon load resistors, in said contact holes, in said composite interlevel dielectric layer.

Claim 2

A method of fabricating a MOSFET device, for a SRAM cell, on a semiconductor substrate, using a self-aligned, halo, (SAC halo), implant region, in said MOSFET device, comprising the steps of: forming field oxide regions in said semiconductor substrate; growing a gate insulator layer on said semiconductor substrate, in areas not covered by said field oxide regions; depositing a first polysilicon layer on said gate insulator layer; depositing a first metal silicide layer on said first polysilicon layer; depositing a first insulator layer on said first metal silicide layer; patterning of said first insulator layer, of said first metal silicide layer, and of said first polysilicon layer, to form polycide gate structures, on said gate insulator layer; ion implanting a first conductivity imparting dopant into said semiconductor substrate, in regions not covered by said polycide gate structures, to form a lightly doped source and drain region; depositing a second insulator layer; anisotropic etching of said second insulator layer to form insulator spacers on the sides of said polycide gate structures; ion implanting a second conductivity imparting dopant into said semiconductor substrate, in regions not covered by said polycide gate structures, or not covered by said insulator spacers, to form a heavily doped source and drain region; depositing a third insulator layer; opening a hole in said third insulator layer, creating a self-aligned contact, (SAC), opening, exposing said heavily doped source and drain region, in said semiconductor substrate, in the space between said polycide gate structures, with said insulator spacers; ion implanting a third conductivity imparting dopant into said SAC opening, to create said SAC halo implant region, in said semiconductor substrate, in space between said polycide structures; depositing a second polysilicon layer, including deposition on said heavily doped source and drain region, and on said SAC halo implant region, in said SAC opening, in space between said polycide gate structures; depositing a second metal silicide layer on said second polysilicon layer; patterning of said second metal silicide layer, and of said second polysilicon layer, to create a polycide, self- aligned contact, (SAC), structure, completely overlying said SAC opening, and with said polycide SAC structure partially overlying a portion of said polysilicon gate structures, in regions where said polycide gate structures are adjacent to said SAC opening; depositing a fourth insulator layer; depositing a third polysilicon layer; patterning of said third polysilicon layer to create polysilicon load resistors; depositing a composite interlevel dielectric layer on said semiconductor substrate, including deposition on said polycide SAC structure, and on said polysilicon load resistors; annealing of said composite interlevel dielectric layer; opening contact holes in said composite interlevel dielectric layer, and in said fourth insulator layer, to expose top surface of said polycide SAC structure, and top surface of said polysilicon load resistors; and forming an interconnect metallization structures, overlying and contacting, said polycide SAC structure, and said polysilicon load resistors, in said contact holes, in said composite interlevel dielectric layer.

Claim 18

A method for forming a self-aligned, halo implant region, (SAC halo region), in a MOSFET device, using a self-aligned contact, (SAC), opening, as a mask, to be used for a triple polysilicon SRAM process, on a semiconductor substrate, comprising the steps of: growing a gate insulator layer on said semiconductor substrate; depositing an in situ doped, first polysilicon layer, on said gate insulator layer; depositing a first tungsten silicide layer, on said first polysilicon layer; depositing a first silicon oxide layer on said first tungsten silicide layer; patterning of said first silicon oxide layer, of said first tungsten silicide layer, and of said first polysilicon layer, to from polycide gate structures on underlying, said gate insulator layer; ion implanting a first conductivity imparting dopant into a region of said semiconductor substrate, not covered by said polycide gate structures, to form a lightly doped source and drain region; depositing a second silicon oxide layer; anisotropic etching of said second silicon oxide layer to form silicon oxide spacers on the sides of said polycide gate structures; ion implanting a second conductivity imparting dopant into a region of said semiconductor substrate, not covered by said polycide gate structures, and not covered by said silicon oxide spacers, to form said heavily doped source and drain region in region between said polycide gate structures; depositing a third silicon oxide layer; forming said self-aligned contact, (SAC), opening in said third silicon oxide layer, exposing said heavily doped source and drain region, in region of said semiconductor substrate, between said polycide gate structures and said silicon oxide spacers; ion implanting a third conductivity imparting dopant into a region of said semiconductor substrate, exposed in said SAC opening, to form a SAC halo implant region; depositing an in situ doped, second polysilicon layer, on said semiconductor substrate, including deposition on said heavily doped source and drain region, and on said SAC halo implant region, exposed in SAC opening; depositing a second tungsten silicide layer on said second polysilicon layer; patterning of said second tungsten silicide layer, and of said second polysilicon layer, to form said polycide SAC structure, completely overlying said heavily doped source and drain region, and said SAC halo implant region, in said SAC opening, and partially overlying a portion of the top of said polycide gate structures, in areas where said polycide gate structures abut said SAC opening; depositing a fourth silicon oxide layer; depositing a third polysilicon layer; patterning of said third polysilicon layer to form polysilicon load resistors; depositing a composite interlevel dielectric layer, completely covering said polycide SAC structure, and said polysilicon load resistors; annealing said composite interlevel dielectric layer; opening contact holes in said composite interlevel dielectric layer, and in said fourth silicon oxide layer, exposing top surface of said polycide SAC structure, and top surface of said polysilicon load resistors; and forming an interconnect metallization structures, overlying and contacting, top surface of said polycide SAC structure, and of said polysilicon load resistors, in said contact holes, in said composite interlevel dielectric layer.

Claim 19

A method for forming a self-aligned, halo implant region, (SAC halo region), in a MOSFET device, using a self-aligned contact, (SAC), opening, as a mask, to be used for a triple polysilicon SRAM process, on a semiconductor substrate, comprising the steps of: growing a gate insulator layer on said semiconductor substrate; depositing an in situ doped, first polysilicon layer, on said gate insulator layer; depositing a first tungsten silicide layer, on said first polysilicon layer; depositing a first silicon oxide layer on said first tungsten silicide layer; patterning of said first silicon oxide layer, of said first tungsten silicide layer, and of said first polysilicon layer, to from polycide gate structures on underlying, said gate insulator layer; ion implanting a first conductivity imparting dopant into a region of said semiconductor substrate, not covered by said polycide gate structures, to form a lightly doped source and drain region; depositing a second silicon oxide layer; anisotropic etching of said second silicon oxide layer to form silicon oxide spacers on the sides of said polycide gate structures; ion implanting a second conductivity imparting dopant into a region of said semiconductor substrate, not covered by said polycide gate structures, and not covered by said silicon oxide spacers, to form said heavily doped source and drain region in region between said polycide gate structures; depositing a third silicon oxide layer; forming said self-aligned contact, (SAC), opening in said third silicon oxide layer, exposing said heavily doped source and drain region, in region of said semiconductor substrate, between said polycide gate structures and said silicon oxide spacers; ion implanting a third conductivity imparting dopant into a region of said semiconductor substrate, exposed in said SAC opening, to form a SAC halo implant region; depositing an in situ doped, second polysilicon layer, on said semiconductor substrate, including deposition on said heavily doped source and drain region, and on said SAC halo implant region, exposed in SAC opening; depositing a second tungsten silicide layer on said second polysilicon layer; patterning of said second tungsten silicide layer, and of said second polysilicon layer, to form said polycide SAC structure, completely overlying said heavily doped source and drain region, and said SAC halo implant region, in said SAC opening, and partially overlying a portion of the top of said polycide gate structures, in areas where said polycide gate structures abut said SAC opening; depositing a fourth silicon oxide layer; depositing a third polysilicon layer; patterning of said third polysilicon layer to form polysilicon load resistors; depositing a composite interlevel dielectric layer, completely covering said polycide SAC structure, and said polysilicon load resistors; annealing said composite interlevel dielectric layer; opening contact holes in said composite interlevel dielectric layer, and in said fourth silicon oxide layer, exposing top surface of said polycide SAC structure, and top surface of said polysilicon load resistors; and forming an interconnect metallization structures, overlying and contacting, top surface of said polycide SAC structure, and of said polysilicon load resistors, in said contact holes, in said composite interlevel dielectric layer.