Patent US6247113B1 successfully refreshed from Google Patents.
US6247113B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coprocessor opcode division by data type
Assignee: ARM Ltd
•
Filing: 1998-05-27
•
Granted: 2001-06-12
•
Expires: 2018-05-27
Abstract
Abstract A data processing system having a main processor and a coprocessor. The main processor responsds to coprocessor instructions within its instruction stream by issuing the coprocessor instructions upon a coprocessor bus and detecting if the coprocessor accepts them by returning an accept signal. The coprocessor instructions include a coprocessor number and the coprocessor checks this number to see if it matches its own number(s) to determine whether or not it should accept the coprocessor instruction. A data type field within the coprocessor number in the coprocessor instruction also serves to specify one of multiple data types to be used in the coprocessor operation; particular coprocessors can interpret this part of the coprocessor number to determine data type. If the coprocessor supports multiple data types, then it has multiple coprocessor numbers for which it will issue accept signals and then uses the data type field to control the data type used. If a coprocessor does not support a particular data type then it will not issue an accept signal for coprocessor instructions that specify that data type. The main processor can then use emulation code to provide support for that coprocessor instruction.
Inventors
- 👤 David Vivian Jaggar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:17
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30192; G06F9/30098; G06F9/30105; G06F9/30112; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
218 words
An apparatus for processing data, said apparatus comprising: a main processor for performing data processing in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction that has: an opcode specifying a data processing operation to be performed by a coprocessor; and a coprocessor identification field for identifying a target coprocessor for said coprocessor instruction; wherein at least one bit of said coprocessor identification field also serves as a data type field indicating a data type to be used in said data processing operation; a coprocessor coupled to said main processor by a bus, said main processor being responsive to a coprocessor instruction to issue at least a representation of said coprocessor instruction upon said bus and said coprocessor being responsive to said coprocessor instruction upon said bus to compare said coprocessor identification field with at least one coprocessor number value identifying said coprocessor and to issue an accept signal to said main processor via said bus if said coprocessor is said target processor; wherein if said coprocessor is a multiple data type coprocessor that supports multiple data types, then it has multiple coprocessor number values, issues an accept signal for any of said multiple coprocessor number values and uses said data type field to control the data type used.
Claim 2
Independent Claim
218 words
An apparatus for processing data, said apparatus comprising: a main processor for performing data processing in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction that has: an opcode specifying a data processing operation to be performed by a coprocessor; and a coprocessor identification field for identifying a target coprocessor for said coprocessor instruction; wherein at least one bit of said coprocessor identification field also serves as a data type field indicating a data type to be used in said data processing operation; a coprocessor coupled to said main processor by a bus, said main processor being responsive to a coprocessor instruction to issue at least a representation of said coprocessor instruction upon said bus and said coprocessor being responsive to said coprocessor instruction upon said bus to compare said coprocessor identification field with at least one coprocessor number value identifying said coprocessor and to issue an accept signal to said main processor via said bus if said coprocessor is said target processor; wherein if said coprocessor is a multiple data type coprocessor that supports multiple data types, then it has multiple coprocessor number values, issues an accept signal for any of said multiple coprocessor number values and uses said data type field to control the data type used.
Claim 3
Dependent Claim
62 words
Apparatus for data processing as claimed in claim 1 , wherein if said coprocessor is a single data type coprocessor that supports a single data type, then it does not issue an accept signal for any coprocessor number value including a data type field corresponding to an unsupported data type and uses said supported data type independent of said data type field.
Claim 4
Dependent Claim
28 words
Apparatus as claimed in claim 1 , wherein said multiple data type coprocessor supports less than all data type that may be specified by said data type field.
Claim 5
Dependent Claim
16 words
Apparatus as claimed in claim 1 , wherein said opcode is independent of said data type.
Claim 6
Dependent Claim
33 words
Apparatus as claimed in claim 1 , wherein said data type field indicates whether said data type is single precision data or double precision data and said coprocessor is a floating point unit.
Claim 7
Dependent Claim
45 words
Apparatus as claimed in claim 1 , wherein said main processor is responsive to said at least one bit of said coprocessor identification field to determine a data type for a data processing operation to be performed together by said main processor and said coprocessor.
Claim 8
Dependent Claim
21 words
Apparatus as claimed in claim 1 , wherein said at least a representation of said coprocessor instruction is said coprocessor instruction.
Claim 9
Dependent Claim
47 words
Apparatus as claimed in claim 1 , wherein if said coprocessor does not issue an accept signal due to an unsupported data type being specified by said data type field then said main processor uses emulation code to emulate said coprocessor instruction for said unsupported data type.
Claim 10
Independent Claim
209 words
A method of processing data with a main processor and a coprocessor, said method comprising the steps of: performing data processing with said main processor in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction that has; an opcode specifying a data processing operation to be performed by said coprocessor; and a coprocessor identification field for identifying a target coprocessor for said coprocessor instruction; wherein at least one bit of said coprocessor identification field also serves as a data type field indicating a data type to be used in said data processing operation; in response to a coprocessor instruction, said main processor issuing at least a representation of said coprocessor instruction upon to said coprocessor; in response to said coprocessor instruction, said coprocessor comparing said coprocessor identification field with at least one coprocessor number value identifying said coprocessor and issuing an accept signal to said main processor if said coprocessor is said target processor; wherein if said coprocessor is a multiple data type coprocessor that supports multiple data types, then it has multiple coprocessor number values, issues an accept signal for any of said multiple coprocessor number values and uses said data type field to control the data type used.
Claim 11
Independent Claim
209 words
A method of processing data with a main processor and a coprocessor, said method comprising the steps of: performing data processing with said main processor in response to a stream of data processing instructions, said data processing instructions including at least one coprocessor instruction that has; an opcode specifying a data processing operation to be performed by said coprocessor; and a coprocessor identification field for identifying a target coprocessor for said coprocessor instruction; wherein at least one bit of said coprocessor identification field also serves as a data type field indicating a data type to be used in said data processing operation; in response to a coprocessor instruction, said main processor issuing at least a representation of said coprocessor instruction upon to said coprocessor; in response to said coprocessor instruction, said coprocessor comparing said coprocessor identification field with at least one coprocessor number value identifying said coprocessor and issuing an accept signal to said main processor if said coprocessor is said target processor; wherein if said coprocessor is a multiple data type coprocessor that supports multiple data types, then it has multiple coprocessor number values, issues an accept signal for any of said multiple coprocessor number values and uses said data type field to control the data type used.
References Cited (Backward Citations)
EP0123337A2
Cited
US5021991A
Cited
EP0299075A1
Cited
US5125095A
Cited
US5093908A
Cited
US5673407A
Cited
US5857096A
Cited
US5778247A
Cited
US5923893A
Cited
US5983338A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-06-11 | 2004-12-11 | 2005-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-06-11 | 2008-12-11 | 2009-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-06-11 | 2012-12-11 | 2013-06-12 | $7700.00 | Window Closed / Lapsed |