EP0123337A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A method and apparatus for coordinating execution of an instruction by a coprocessor
Assignee: Motorola Solutions Inc
•
Filing: 1984-03-26
•
Granted: —
•
Expires: 2004-03-26
Abstract
Abstract A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support ofthe Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
Inventors
- 👤 John Zolnosky
- 👤 David Mothersole
- 👤 Douglas B. Macgregor
- 👤 Michael Gruess
- 👤 Stanley E. Groves
- 👤 Van B. Shahan
- 👤 Donald L. Tietjen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 07:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3877; G06F9/3879; G06F9/3881
Claims Analysis
Total Claims: 133
Claim 1
Independent Claim
92 words
A method for coordinating from a first data processor the execution by a second data processor of an instruction received for execution by said first processor, comprising the steps of: receiving said instruction; writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; reading a response from said second processor; and selectively performing a predetermined task if said response indicates that said task must be performed by said first processor in support of the execution of said instruction by said second processor.
Claim 2
Independent Claim
92 words
A method for coordinating from a first data processor the execution by a second data processor of an instruction received for execution by said first processor, comprising the steps of: receiving said instruction; writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; reading a response from said second processor; and selectively performing a predetermined task if said response indicates that said task must be performed by said first processor in support of the execution of said instruction by said second processor.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein the step of performing said task comprises performing a particular one of a plurality of predetermined tasks selected by said response.
Claim 4
Dependent Claim
30 words
The method of claim 1 wherein said step of reading comprises repeatedly reading a response from said second processor until said response indicates that said second processor is not busy.
Claim 5
Dependent Claim
27 words
The method of claim 3 wherein said step of performing said task comprises performing a particular one of a plurality of predetermined tasks selected by said response.
Claim 6
Dependent Claim
48 words
The method of claim 1 further comprising the step of repeating the steps of reading said response and performing said tasks until said response indicates that no further tasks must be performed by said first processor in support of the execution of said instruction by said second processor.
Claim 7
Dependent Claim
99 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received for execution by said first processor: first means for receiving said instruction; second means for writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; third means for reading a response from said second processor; and fourth means for selectively performing a predetermined task if said response indicates that said task must be performed by said first processor in support of the execution of said instruction by said second processor.
Claim 8
Dependent Claim
99 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received for execution by said first processor: first means for receiving said instruction; second means for writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; third means for reading a response from said second processor; and fourth means for selectively performing a predetermined task if said response indicates that said task must be performed by said first processor in support of the execution of said instruction by said second processor.
Claim 9
Dependent Claim
28 words
The data processor of claim 6 wherein said fourth means are further characterized as performing a particular one of a plurality of predetermined tasks selected by said response.
Claim 10
Dependent Claim
29 words
The data processor of claim 6 wherein said third means repeatedly reads a response from said second processor until said response indicates that said second processor is not busy.
Claim 11
Dependent Claim
28 words
The data processor of claim 8 wherein said fourth means are further characterized as performing a particular one of a plurality of predetermined tasks selected by said response.
Claim 12
Dependent Claim
49 words
The data processor of claim 6 wherein said third and fourth means continue to read said responses and to perform said tasks until said response indicates that no further tasks must be performed by said first processor in support of the execution of said instruction by said second processor.
Claim 13
Independent Claim
110 words
A method for a first data processor to cooperate with a second data processor to execute an instruction received for execution by said second processor, comprising the steps of: receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; determining from the received portion of said instruction if a predetermined task must be performed by said second processor in support of the execution of said instruction by said first processor; and providing to said second processor a response indicating that said task must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 14
Independent Claim
110 words
A method for a first data processor to cooperate with a second data processor to execute an instruction received for execution by said second processor, comprising the steps of: receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; determining from the received portion of said instruction if a predetermined task must be performed by said second processor in support of the execution of said instruction by said first processor; and providing to said second processor a response indicating that said task must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 15
Dependent Claim
52 words
The method of claim 11 wherein said step of determining is further characterized as determining from the received portion of said instruction which of a particular one of a plurality of predetermined tasks must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 16
Dependent Claim
34 words
The method of claim 11 wherein said step of providing said response includes providing a response to said second processor indicating that said first processor is busy until said first processor is not busy.
Claim 17
Dependent Claim
52 words
The method of claim 13 wherein said step of determining is further characterized as determining from the received portion of said instruction which of a particular one of a plurality of predetermined tasks must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 18
Dependent Claim
56 words
The method of claim 11 wherein said steps of determining and providing are repeated to determine which tasks must be performed and to provide said responses indicating that said tasks must be performed, until no further tasks must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 19
Dependent Claim
114 words
In a first data processor adapted for cooperating with a second data processor to execute an instruction received for execution by said second processor: first means for receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; second means for determining from the received portion of said instruction if a predetermined task must be performed by said second processor in support of the execution of said instruction by said first processor; and third means for providing to said second processor a response indicating that said task must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 20
Dependent Claim
114 words
In a first data processor adapted for cooperating with a second data processor to execute an instruction received for execution by said second processor: first means for receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; second means for determining from the received portion of said instruction if a predetermined task must be performed by said second processor in support of the execution of said instruction by said first processor; and third means for providing to said second processor a response indicating that said task must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 21
Dependent Claim
52 words
The data processor of claim 16 wherein said second means are further characterized as determining from the received portion of said instruction which of a particular one of a plurality of predetermined tasks must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 22
Dependent Claim
32 words
The data processor of claim 16 wherein said third means repeatedly provides a response to said second processor indicating that said first processor is busy until said first processor is not busy.
Claim 23
Dependent Claim
52 words
The data processor of claim 18 wherein said second means are further characterized as determining from the received portion of said instruction which of a particular one of a plurality of predetermined tasks must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 24
Dependent Claim
55 words
The data processor of claim 16 wherein said second and third means continue to determine which tasks must be performed and to provide said responses indicating that said tasks must be performed, until no further tasks must be performed by said second processor in support of the execution of said instruction by said first processor.
Claim 25
Independent Claim
77 words
A system for instructing a processor to cooperate with a coprocessor in the execution of a selected function, in which an instruction comprises: a command signal which defines said selected function; and an operation signal which instructs said processor to transfer said command signal to said coprocessor, and to selectively perform at least one predetermined task at the request of said coprocessor in support of the execution by said coprocessor of the function defined by said command.
Claim 26
Independent Claim
77 words
A system for instructing a processor to cooperate with a coprocessor in the execution of a selected function, in which an instruction comprises: a command signal which defines said selected function; and an operation signal which instructs said processor to transfer said command signal to said coprocessor, and to selectively perform at least one predetermined task at the request of said coprocessor in support of the execution by said coprocessor of the function defined by said command.
Claim 27
Dependent Claim
64 words
The system of claim 21 wherein said processor may be instructed to cooperate with any of a plurality of coprocessors in the execution of said selected function, and wherein each of said instructions further comprises: a coprocessor identification signal which identifies to said processor the particular one of said coprocessors with which said processor is to cooperate in the execution of said selected function.
Claim 28
Independent Claim
154 words
A method for a first data processor to coordinate with a second data processor the execution of each of a predetermined subset of instructions received for execution by said first data processor comprising the steps of: receiving instructions for execution by said first data processor; detecting in a predetermined operation portion of each of said received instructions an indication characteristic of each and every one of said instructions comprising said subset; writing to said second processor a predetermined portion of each of said detected instructions which contains a command which must be performed by said second processor in support of the execution of said detected instruction by said first processor; reading from said second processor a response to said command which indicates whether a predetermined task must be performed by said first processor in support of the performance of said command by said second processor; and performing said task if indicated by said response.
Claim 29
Independent Claim
154 words
A method for a first data processor to coordinate with a second data processor the execution of each of a predetermined subset of instructions received for execution by said first data processor comprising the steps of: receiving instructions for execution by said first data processor; detecting in a predetermined operation portion of each of said received instructions an indication characteristic of each and every one of said instructions comprising said subset; writing to said second processor a predetermined portion of each of said detected instructions which contains a command which must be performed by said second processor in support of the execution of said detected instruction by said first processor; reading from said second processor a response to said command which indicates whether a predetermined task must be performed by said first processor in support of the performance of said command by said second processor; and performing said task if indicated by said response.
Claim 30
Dependent Claim
164 words
In a first data processor adapted for coordinating with a second data processor the execution of each of a predetermined subset of instructions received for execution by said first data processor: first means for receiving instructions for execution by said first data processor; second means for detecting in a predetermined operation portion of each of said received instructions an indication characteristic of each and every one of said instructions comprising said subset; third means for writing to said second processor a predetermined portion of each of said detected instructions which contains a command which must be performed by said second processor in support of the execution of said detected instruction by said first processor; fourth means for reading from said second processor a response to said command which indicates whether a predetermined task must be performed by said first processor in support of the performance of said command by said second processor; and fifth means for performing said task if indicated by said response.
Claim 31
Dependent Claim
164 words
In a first data processor adapted for coordinating with a second data processor the execution of each of a predetermined subset of instructions received for execution by said first data processor: first means for receiving instructions for execution by said first data processor; second means for detecting in a predetermined operation portion of each of said received instructions an indication characteristic of each and every one of said instructions comprising said subset; third means for writing to said second processor a predetermined portion of each of said detected instructions which contains a command which must be performed by said second processor in support of the execution of said detected instruction by said first processor; fourth means for reading from said second processor a response to said command which indicates whether a predetermined task must be performed by said first processor in support of the performance of said command by said second processor; and fifth means for performing said task if indicated by said response.
Claim 32
Independent Claim
133 words
A method for a first data processor to cooperate with a second data processor to execute each of a predetermined subset of instructions received for execution by said second data processor comprising the steps of: receiving from said second data processor that portion of each of said subset of instructions which contains a command which must be performed by said first processor in support of the execution of said instruction by said first processor; determining from said received command whether a predetermined task must be performed by said second processor in support of the performance of said command by said first processor; and providing to said second processor a response indicating that said task must be performed by said second processor in support of the performance of said command by said first processor.
Claim 33
Independent Claim
133 words
A method for a first data processor to cooperate with a second data processor to execute each of a predetermined subset of instructions received for execution by said second data processor comprising the steps of: receiving from said second data processor that portion of each of said subset of instructions which contains a command which must be performed by said first processor in support of the execution of said instruction by said first processor; determining from said received command whether a predetermined task must be performed by said second processor in support of the performance of said command by said first processor; and providing to said second processor a response indicating that said task must be performed by said second processor in support of the performance of said command by said first processor.
Claim 34
Dependent Claim
137 words
In a first data processor adapted for cooperating with a second data processor to execute each of a predetermined subset of instructions received for execution by said second data processor: first means for receiving from said second data processor that portion of each of said subset of instructions which contains a command which must be performed by said first processor in support of the execution of said instruction by said first processor; second means for determining from said received command whether a predetermined task must be performed by said second processor in support of the performance of said command by said first processor; and third means for providing to said second processor a response indicating that said task must be performed by said second processor in support of the performance of said command by said first processor.
Claim 35
Dependent Claim
137 words
In a first data processor adapted for cooperating with a second data processor to execute each of a predetermined subset of instructions received for execution by said second data processor: first means for receiving from said second data processor that portion of each of said subset of instructions which contains a command which must be performed by said first processor in support of the execution of said instruction by said first processor; second means for determining from said received command whether a predetermined task must be performed by said second processor in support of the performance of said command by said first processor; and third means for providing to said second processor a response indicating that said task must be performed by said second processor in support of the performance of said command by said first processor.
Claim 36
Dependent Claim
83 words
In a first data processor adapted for coordinating the execution by an addressable second data processor of an instruction received for execution by said first data processor: first means for receiving said instruction; second means for providing an address for addressing said second processor using as a portion of such address a portion of said instruction received by said first means; and third means for coordinating the execution of said instruction by said second processor at the address provided by said second means.
Claim 37
Dependent Claim
83 words
In a first data processor adapted for coordinating the execution by an addressable second data processor of an instruction received for execution by said first data processor: first means for receiving said instruction; second means for providing an address for addressing said second processor using as a portion of such address a portion of said instruction received by said first means; and third means for coordinating the execution of said instruction by said second processor at the address provided by said second means.
Claim 38
Independent Claim
68 words
A method for a first processor to coordinate the execution by an addressable second data processor of an instruction received for execution by said first data processor, comprising the steps of: receiving said instruction; providing an address for addressing said second processor using as a portion of such address a portion of said instruction; and coordinating the execution of said instruction by said second processor at said address.
Claim 39
Independent Claim
68 words
A method for a first processor to coordinate the execution by an addressable second data processor of an instruction received for execution by said first data processor, comprising the steps of: receiving said instruction; providing an address for addressing said second processor using as a portion of such address a portion of said instruction; and coordinating the execution of said instruction by said second processor at said address.
Claim 40
Dependent Claim
89 words
In a first data processor adapted for coordinating the execution of an instruction received for execution by said first data processor with a second data processor responsive to a unique address: first means for receiving said instruction; second means for providing said unique address by including as a portion of a general address a predetermined portion of said received instruction which uniquely identifies said second processor; and third means for coordinating the execution of said instruction by said second processor at the unique address provided by said second means.
Claim 41
Dependent Claim
89 words
In a first data processor adapted for coordinating the execution of an instruction received for execution by said first data processor with a second data processor responsive to a unique address: first means for receiving said instruction; second means for providing said unique address by including as a portion of a general address a predetermined portion of said received instruction which uniquely identifies said second processor; and third means for coordinating the execution of said instruction by said second processor at the unique address provided by said second means.
Claim 42
Dependent Claim
89 words
The data processor of claim 29 wherein said second data processor is further characterized as containing a plurality of registers which may be required by said second data processor in the execution of said instruction, with each of said registers being responsive to a respective address within a range of addresses unique to said second data processor; and wherein said second means provides said respective addresses as each of said registers is required by said third means in coordinating the execution of said instruction by said second data processor.
Claim 43
Independent Claim
85 words
A method for a first data processor to coordinate the execution of an instruction received for execution by said first data processor with a second data processor responsive to a unique address, comprising the steps of: receiving said instruction; providing said unique address by including as a portion of a general address a predetermined portion of said received instruction which uniquely identifies said second processor; and coordinating the execution of said instruction by said second processor at the unique address provided by said second means.
Claim 44
Independent Claim
85 words
A method for a first data processor to coordinate the execution of an instruction received for execution by said first data processor with a second data processor responsive to a unique address, comprising the steps of: receiving said instruction; providing said unique address by including as a portion of a general address a predetermined portion of said received instruction which uniquely identifies said second processor; and coordinating the execution of said instruction by said second processor at the unique address provided by said second means.
Claim 45
Dependent Claim
86 words
The method of claim 31 wherein said second data processor is further characterized as containing a plurality of registers which may be required by said second data processor in the execution of said instruction, with each of said registers being responsive to a respective address within a range of addresses unique to said second data processor; and wherein said step of providing comprises providing said respective addresses as each of said registers is required in coordinating the execution of said instruction by said second data processor.
Claim 46
Dependent Claim
100 words
In a first data processor adapted for executing an instruction contingent upon a condition existing in a second data processor: first means for receiving said instruction; second means for determining a condition upon which the execution of said instruction is contingent; third means for writing to said second processor a request that said second processor evaluate said condition and provide an indication of whether, as a result of said evaluation, said condition was determined by said second processor to have been satisfied; fourth means for reading said indication; and fifth means for selectively executing said instruction based upon said indication.
Claim 47
Dependent Claim
100 words
In a first data processor adapted for executing an instruction contingent upon a condition existing in a second data processor: first means for receiving said instruction; second means for determining a condition upon which the execution of said instruction is contingent; third means for writing to said second processor a request that said second processor evaluate said condition and provide an indication of whether, as a result of said evaluation, said condition was determined by said second processor to have been satisfied; fourth means for reading said indication; and fifth means for selectively executing said instruction based upon said indication.
Claim 48
Independent Claim
90 words
A method for a first data processor to execute an instruction contingent upon a condition existing in a second data processor, comprising the steps of: receiving said instruction; determining a condition upon which the execution of said instruction is contingent; writing to said second processor a request that said second processor evaluate said condition and provide an indication of whether, as a result of said evaluation, said condition was determined by said second processor to have been satisfied; reading said indication; and selectively executing said instruction based upon said indication.
Claim 49
Independent Claim
90 words
A method for a first data processor to execute an instruction contingent upon a condition existing in a second data processor, comprising the steps of: receiving said instruction; determining a condition upon which the execution of said instruction is contingent; writing to said second processor a request that said second processor evaluate said condition and provide an indication of whether, as a result of said evaluation, said condition was determined by said second processor to have been satisfied; reading said indication; and selectively executing said instruction based upon said indication.
Claim 50
Dependent Claim
92 words
In a first data processor adapted for cooperating with a second data processor in the execution by said second processor of an instruction contingent upon a condition existing in said first data processor: first means for receiving from said second processor a request that said first processor evaluate the condition upon which the execution of said instruction by said second processor is contingent; second means for evaluating said condition; and third means for providing an indication of whether, as a result of said evaluation, said condition was determined to have been satisfied.
Claim 51
Dependent Claim
92 words
In a first data processor adapted for cooperating with a second data processor in the execution by said second processor of an instruction contingent upon a condition existing in said first data processor: first means for receiving from said second processor a request that said first processor evaluate the condition upon which the execution of said instruction by said second processor is contingent; second means for evaluating said condition; and third means for providing an indication of whether, as a result of said evaluation, said condition was determined to have been satisfied.
Claim 52
Independent Claim
88 words
A method for a first data processor to cooperate with a second data processor in the execution by said second processor of an instruction contingent upon a condition existing in said first data processor, comprising the steps of: receiving from said second processor a request that said first processor evaluate the condition upon which the execution of said instruction by said second processor is contingent; evaluating said condition; and providing an indication of whether, as a result of said evaluation, said condition was determined to have been satisfied.
Claim 53
Independent Claim
88 words
A method for a first data processor to cooperate with a second data processor in the execution by said second processor of an instruction contingent upon a condition existing in said first data processor, comprising the steps of: receiving from said second processor a request that said first processor evaluate the condition upon which the execution of said instruction by said second processor is contingent; evaluating said condition; and providing an indication of whether, as a result of said evaluation, said condition was determined to have been satisfied.
Claim 54
Independent Claim
87 words
A method for coordinating from a first data processor the execution by a second data processor of an instruction received for execution by said first processor, comprising the steps of: receiving said instruction; writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; reading a response from said second processor; and vectoring to a predetermined exception handler if said response indicates that an exception has been detected by said second processor during said execution of said instruction.
Claim 55
Independent Claim
87 words
A method for coordinating from a first data processor the execution by a second data processor of an instruction received for execution by said first processor, comprising the steps of: receiving said instruction; writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; reading a response from said second processor; and vectoring to a predetermined exception handler if said response indicates that an exception has been detected by said second processor during said execution of said instruction.
Claim 56
Dependent Claim
30 words
The method of claim 37 wherein said step of reading comprises repeatedly reading a response from said second processor until said response indicates that said second processor is not busy.
Claim 57
Dependent Claim
38 words
The method of claim 37 wherein the response also indicates an exception vector number corresponding to said exception handler, and wherein the step of vectoring includes determining from said exception vector number the address of said exception handler.
Claim 58
Dependent Claim
94 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received for execution by said first processor: first means for receiving said instruction; second means for writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; third means for reading a response from said second processor; and fourth means for vectoring to a predetermined exception handler if said response indicates that an exception has been detected by said second processor during said execution of said instruction.
Claim 59
Dependent Claim
94 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received for execution by said first processor: first means for receiving said instruction; second means for writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; third means for reading a response from said second processor; and fourth means for vectoring to a predetermined exception handler if said response indicates that an exception has been detected by said second processor during said execution of said instruction.
Claim 60
Dependent Claim
29 words
The data processor of claim 40 wherein the third means repeatedly reads a response from said second processor until said response indicates that said second processor is not busy.
Claim 61
Dependent Claim
37 words
The data processor of claim 41 wherein the response also indicates an exception vector number corresponding to said exception handler, and wherein the fourth means determine from said exception vector number the address of said exception handler.
Claim 62
Independent Claim
109 words
A method for a first data processor to cooperate with a second data processor in the execution by said first data processor of an instruction received for execution by said second processor, comprising the steps of: receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; executing said instruction; detecting an exception in the execution of said instruction; and providing a response to said second processor which indicates to said second processor that said exception has been detected by said first processor during said execution of said instruction and that said second processor should vector to a predetermined exception handler.
Claim 63
Independent Claim
109 words
A method for a first data processor to cooperate with a second data processor in the execution by said first data processor of an instruction received for execution by said second processor, comprising the steps of: receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; executing said instruction; detecting an exception in the execution of said instruction; and providing a response to said second processor which indicates to said second processor that said exception has been detected by said first processor during said execution of said instruction and that said second processor should vector to a predetermined exception handler.
Claim 64
Dependent Claim
34 words
The method of claim 43 wherein said step of providing said response includes repeatedly providing a response to said second processor that said first processor is busy until said first processor is not busy.
Claim 65
Dependent Claim
19 words
The method of claim 43 wherein the response also indicates an exception vector number corresponding to said exception handler.
Claim 66
Dependent Claim
116 words
In a first data processor adapted for cooperating with a second data processor in the execution by said first data processor of an instruction received for execution by said second processor: first means for receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; second means for executing said instruction; third means for detecting an exception in the execution of said instruction; and fourth means for providing a response to said second processor which indicates to said second processor that said exception has been detected by said first processor during said execution of said instruction and that said second processor should vector to a predetermined exception handler.
Claim 67
Dependent Claim
116 words
In a first data processor adapted for cooperating with a second data processor in the execution by said first data processor of an instruction received for execution by said second processor: first means for receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; second means for executing said instruction; third means for detecting an exception in the execution of said instruction; and fourth means for providing a response to said second processor which indicates to said second processor that said exception has been detected by said first processor during said execution of said instruction and that said second processor should vector to a predetermined exception handler.
Claim 68
Dependent Claim
32 words
The data processor of claim 46 wherein the fourth means repeatedly provides a response to said second processor indicating that said first processor is busy until said first processor is not busy.
Claim 69
Dependent Claim
20 words
The data processor of claim 46 wherein the response also indicates an exception vector number corresponding to said exception handler.
Claim 70
Dependent Claim
73 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received by said first data processor: first means for receiving said instruction; second means for commanding said second processor to execute said received instruction; third means for selectively interrupting said execution of said instruction by said second processor; and fourth means for storing the state of said second processor at the time of said interruption.
Claim 71
Dependent Claim
73 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received by said first data processor: first means for receiving said instruction; second means for commanding said second processor to execute said received instruction; third means for selectively interrupting said execution of said instruction by said second processor; and fourth means for storing the state of said second processor at the time of said interruption.
Claim 72
Dependent Claim
24 words
The data processor of claim 49 wherein the third means interrupts said execution by reading a predetermined addressable location within said second data processor.
Claim 73
Dependent Claim
33 words
The data processor of claim 49 wherein said fourth means reads the state of said second processor from a predetermined addressable location within said second data processor and stores said state so read.
Claim 74
Dependent Claim
23 words
The data processor of claim 51 further including fifth means for selectively restoring the state of said second processor to said stored state.
Claim 75
Dependent Claim
30 words
The data processor of claim 52 wherein said fifth means reads said stored state and writes the stored state so read to said predetermined addressable location within said second processor.
Claim 76
Dependent Claim
23 words
The data processor of claim 49 further including fifth means for selectively restoring the state of said second processor to said stored state.
Claim 77
Dependent Claim
77 words
In a first data processor adapted for cooperating with a second data processor to execute an instruction received by said second data processor: first means for receiving a command from said second data processor to execute said instruction; second means for interrupting said execution in response to being interrupted by said second data processor; and third means for providing to said second data processor the state of said first data processor at the time of said interruption.
Claim 78
Dependent Claim
77 words
In a first data processor adapted for cooperating with a second data processor to execute an instruction received by said second data processor: first means for receiving a command from said second data processor to execute said instruction; second means for interrupting said execution in response to being interrupted by said second data processor; and third means for providing to said second data processor the state of said first data processor at the time of said interruption.
Claim 79
Dependent Claim
29 words
The data processor of claim 55 wherein the second means interrupts said execution in response to said second processor reading a predetermined addressable location within said first data processor.
Claim 80
Dependent Claim
26 words
The data processor of claim 55 wherein said third means provides the state of said first processor via a predetermined addressable location within said first processor.
Claim 81
Dependent Claim
39 words
'The data processor of claim 57 further including: fourth means for receiving from said second processor the state of said first processor provided to said second processor; and fifth means for restoring said first processor to the received state.
Claim 82
Dependent Claim
26 words
The data processor of claim 58 wherein said fourth means receives said state from said second processor via said predetermined addressable location within said first processor.
Claim 83
Dependent Claim
39 words
The data processor of claim 55 further including: fourth means for receiving from said second processor the state of said first processor provided to said second processor; and fifth means for restoring said first processor to the received state.
Claim 84
Independent Claim
59 words
A method for a first data processor to coordinate the execution by a second data processor of an instruction received by said first data processor, comprising the steps of: receiving said instruction; commanding said second processor to execute said received instruction; selectively interrupting said execution; and storing the state of said second processor at the time of said interruption.
Claim 85
Independent Claim
59 words
A method for a first data processor to coordinate the execution by a second data processor of an instruction received by said first data processor, comprising the steps of: receiving said instruction; commanding said second processor to execute said received instruction; selectively interrupting said execution; and storing the state of said second processor at the time of said interruption.
Claim 86
Dependent Claim
25 words
The method of claim 61 wherein the step of interrupting comprises interrupting said execution by reading a predetermined addressable location within said second data processor.
Claim 87
Dependent Claim
34 words
The method of claim 61 wherein the step of storing comprises reading the state of said second processor from a predetermined addressable location within said second data processor and storing said state so read.
Claim 88
Dependent Claim
22 words
The method of claim 63 further including the step of selectively restoring the state of said second processor to said stored state.
Claim 89
Dependent Claim
31 words
The method of claim 64 wherein said step of restoring comprises reading said stored state and writing the stored state so read to said predetermined addressable location within said second processor.
Claim 90
Dependent Claim
22 words
The method of claim 61 further including the step of selectively restoring the state of said second processor to said stored state.
Claim 91
Independent Claim
73 words
A method for a first data processor to cooperate with a second data processor to execute an instruction received by said second data processor, comprising the steps of: receiving a command from said second data processor to execute said instruction; interrupting said execution in response to being interrupted by said second data processor; and providing to said second data processor the state of said first data processor at the time of said interruption.
Claim 92
Independent Claim
73 words
A method for a first data processor to cooperate with a second data processor to execute an instruction received by said second data processor, comprising the steps of: receiving a command from said second data processor to execute said instruction; interrupting said execution in response to being interrupted by said second data processor; and providing to said second data processor the state of said first data processor at the time of said interruption.
Claim 93
Dependent Claim
30 words
The method of claim 67 wherein the step of interrupting comprises interrupting said execution in response to said second processor reading a predetermined addressable location within said first data processor.
Claim 94
Dependent Claim
27 words
The method of claim 67 wherein the step of providing comprises providing the state of said first processor via a predetermined addressable location within said first processor.
Claim 95
Dependent Claim
35 words
The method of claim 69 further including the steps of receiving from said second processor the state of said first processor provided to said second processor and restoring said first processor to the received state.
Claim 96
Dependent Claim
29 words
The method of claim 70 wherein said step of receiving said state comprises receiving said state from said second processor via said predetermined addressable location within said first processor.
Claim 97
Dependent Claim
36 words
The data processor of claim 67 further including the steps of receiving from said second processor the state of said first processor provided to said second processor and restoring said first processor to the received state.
Claim 98
Dependent Claim
117 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received by said first data processor: first means for receiving said instruction; second means for commanding said second processor to execute said received instruction; third means for selectively requesting said second processor to interrupt said execution; fourth means for receiving from said second processor an indication that said requested interrupt must be delayed; fifth means for periodically polling said second processor during the period of said delay to determine when said second processor interrupts said execution; sixth means for reading the state of said second processor at the time of said interruption; and seventh means for storing said state.
Claim 99
Dependent Claim
117 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received by said first data processor: first means for receiving said instruction; second means for commanding said second processor to execute said received instruction; third means for selectively requesting said second processor to interrupt said execution; fourth means for receiving from said second processor an indication that said requested interrupt must be delayed; fifth means for periodically polling said second processor during the period of said delay to determine when said second processor interrupts said execution; sixth means for reading the state of said second processor at the time of said interruption; and seventh means for storing said state.
Claim 100
Dependent Claim
23 words
The data processor of claim 73 further including eighth means for selectively restoring the state of said second processor to said stored state.
Claim 101
Independent Claim
100 words
A method for a first data processor to coordinate the execution by a second data processor of an instruction received by said first data processor, comprising the steps of: receiving said instruction; commanding said second processor to execute said received instruction; requesting said second processor to interrupt said execution; receiving from said second processor an indication that said requested interrupt must be delayed; periodically polling said second processor during the period of said delay to determine when said second processor interrupts said execution; reading the state o said second processor at the time of said interruption; and storing said state.
Claim 102
Independent Claim
100 words
A method for a first data processor to coordinate the execution by a second data processor of an instruction received by said first data processor, comprising the steps of: receiving said instruction; commanding said second processor to execute said received instruction; requesting said second processor to interrupt said execution; receiving from said second processor an indication that said requested interrupt must be delayed; periodically polling said second processor during the period of said delay to determine when said second processor interrupts said execution; reading the state o said second processor at the time of said interruption; and storing said state.
Claim 103
Dependent Claim
22 words
The method of claim 75 further including the step of selectively restoring the state of said second processor to said stored state.
Claim 104
Dependent Claim
138 words
In a first data processor adapted for cooperating with a second data processor to selectively execute an instruction received by said first data processor: first means for receiving a command from said second processor to execute said instruction; second means for executing said instruction; third means for receiving during said execution a request from said second processor to interrupt said execution; fourth means for determining that said interrupt must be delayed until a predetermined point in said execution; fifth means for providing to said second processor an indication that said requested interrupt must be delayed; sixth means for interrupting said execution at said predetermined point; seventh means for providing to said second processor an indication that said execution has been interrupted; and eighth means for providing the state of said first processor at the time of said interruption.
Claim 105
Dependent Claim
138 words
In a first data processor adapted for cooperating with a second data processor to selectively execute an instruction received by said first data processor: first means for receiving a command from said second processor to execute said instruction; second means for executing said instruction; third means for receiving during said execution a request from said second processor to interrupt said execution; fourth means for determining that said interrupt must be delayed until a predetermined point in said execution; fifth means for providing to said second processor an indication that said requested interrupt must be delayed; sixth means for interrupting said execution at said predetermined point; seventh means for providing to said second processor an indication that said execution has been interrupted; and eighth means for providing the state of said first processor at the time of said interruption.
Claim 106
Dependent Claim
39 words
The data processor of claim 77 further including: ninth means for receiving from said second processor the state of said first processor provided to said second processor; and tenth means for restoring said first processor to the received state.
Claim 107
Independent Claim
119 words
A method for a first data processor to cooperate with a second data processor to selectively execute an instruction received by said second data processor, comprising the steps of: receiving a command from said second processor to execute said instruction; executing said instruction; receiving during said execution a request from said second processor to interrupt said execution; determining that said interrupt must be delayed until a predetermined point in said execution; providing to said second processor an indication that said requested interrupt must be delayed; interrupting said execution at said predetermined point; providing to said second processor an indication that said execution has been interrupted; and providing the state of said first processor at the time of said interruption.
Claim 108
Independent Claim
119 words
A method for a first data processor to cooperate with a second data processor to selectively execute an instruction received by said second data processor, comprising the steps of: receiving a command from said second processor to execute said instruction; executing said instruction; receiving during said execution a request from said second processor to interrupt said execution; determining that said interrupt must be delayed until a predetermined point in said execution; providing to said second processor an indication that said requested interrupt must be delayed; interrupting said execution at said predetermined point; providing to said second processor an indication that said execution has been interrupted; and providing the state of said first processor at the time of said interruption.
Claim 109
Dependent Claim
36 words
The data processor of claim 79 including the further steps of: receiving from said second processor the state of said first processor provided to said second processor; and restoring said first processor to the received state.
Claim 110
Independent Claim
94 words
A method for coordinating from a first data processor the execution by a second data processor of an instruction received for execution by said first processor, comprising the steps of: receiving said instruction; writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; reading a response from said second processor; and evaluating an effective address in said instruction if said response indicates that said address must be evaluated by said first processor in support of the execution of said instruction by said second processor.
Claim 111
Independent Claim
94 words
A method for coordinating from a first data processor the execution by a second data processor of an instruction received for execution by said first processor, comprising the steps of: receiving said instruction; writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; reading a response from said second processor; and evaluating an effective address in said instruction if said response indicates that said address must be evaluated by said first processor in support of the execution of said instruction by said second processor.
Claim 112
Dependent Claim
42 words
The method of claim 81 including the further step of transferring an operand between said second processor and said evaluated effective address if said response also indicates that said transfer is required by said second processor in the execution of said instruction.
Claim 113
Dependent Claim
42 words
The method of claim 81 wherein the step of evaluating comprises: determining from said response a class of effective addresses valid for said instruction; and evaluating an effective address in said instruction only if said effective address is of said valid class.
Claim 114
Dependent Claim
33 words
The method of claim 83 wherein said step of evaluating includes the further step of: providing an error signal to said second processor if said effective address is not of said valid class.
Claim 115
Dependent Claim
42 words
The method of claim 83 including the further step of transferring an operand between said second processor and said evaluated effective address if said response also indicates that said transfer is required by said second processor in the execution of said instruction.
Claim 116
Dependent Claim
101 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received for execution by said first processor: first means for receiving said instruction; second means for writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; third means for reading a response from said second processor; and fourth means for evaluating an effective address in said instruction if said response indicates that said address must be evaluated by said first processor in support of the execution of said instruction by said second processor.
Claim 117
Dependent Claim
101 words
In a first data processor adapted for coordinating the execution by a second data processor of an instruction received for execution by said first processor: first means for receiving said instruction; second means for writing to said second processor at least that portion of said received instruction which indicates the type of said instruction; third means for reading a response from said second processor; and fourth means for evaluating an effective address in said instruction if said response indicates that said address must be evaluated by said first processor in support of the execution of said instruction by said second processor.
Claim 118
Dependent Claim
43 words
The data processor of claim 86 further including fifth means for transferring an operand between said second processor and said evaluated effective address if said response also indicates that said transfer is required by said second processor in the execution of said instruction.
Claim 119
Dependent Claim
48 words
The data processor of claim 86 wherein the fourth means comprise: fifth means for determining from said response a class of effective addresses valid for said instruction; and sixth means for evaluating an effective address in said instruction only if said effective address is of said valid class.
Claim 120
Dependent Claim
33 words
The data processor of claim 88 wherein the fourth means further includes: seventh means for providing an error signal to said second processor if said effective address is not of said valid class.
Claim 121
Dependent Claim
43 words
The data processor of claim 88 further including seventh means for transferring an operand between said second processor and said evaluated effective address if said response also indicates that said transfer is required by said second processor in the execution of said instruction.
Claim 122
Independent Claim
93 words
A method for a first data processor to cooperate with a second data processor in the execution of an instruction received for execution by said second processor, comprising the steps of: receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; determining whether an effective address in said instruction must be evaluated by said second processor in support of the execution of said instruction by said first processor; and providing a response to said second processor indicating that said effective address must be evaluated.
Claim 123
Independent Claim
93 words
A method for a first data processor to cooperate with a second data processor in the execution of an instruction received for execution by said second processor, comprising the steps of: receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; determining whether an effective address in said instruction must be evaluated by said second processor in support of the execution of said instruction by said first processor; and providing a response to said second processor indicating that said effective address must be evaluated.
Claim 124
Dependent Claim
48 words
The method of claim 91 wherein the step of determining includes determining whether an operand must be transferred between said first processor and said evaluated effective address, and wherein said response also indicates that said transfer is required by said first processor in the execution of said instruction.
Claim 125
Dependent Claim
45 words
The method of claim 91 wherein the step of determining includes determining a class of effective addresses valid for said instruction, and wherein said response also indicates that said effective address is to be evaluated only if said effective address is of said valid class.
Claim 126
Dependent Claim
34 words
The method of claim 93 including the further step of: receiving an error signal from said second processor indicating that said second processor determined that said effective address is not of said valid class.
Claim 127
Dependent Claim
48 words
The method of claim 93 wherein the step of determining includes determining whether an operand must be transferred between said first processor and said evaluated effective address, and wherein said response also indicates that said transfer is required by said first processor in the execution of said instruction.
Claim 128
Dependent Claim
97 words
In a first data processor adapted for cooperating with a second data processor in the execution of an instruction received for execution by said second processor: first means for receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; second means for determining whether an effective address in said instruction must be evaluated by said second processor in support of the execution of said instruction by said first processor; and third means for providing a response to said second processor indicating that said effective address must be evaluated.
Claim 129
Dependent Claim
97 words
In a first data processor adapted for cooperating with a second data processor in the execution of an instruction received for execution by said second processor: first means for receiving from said second processor at least that portion of said instruction which indicates the type of said instruction; second means for determining whether an effective address in said instruction must be evaluated by said second processor in support of the execution of said instruction by said first processor; and third means for providing a response to said second processor indicating that said effective address must be evaluated.
Claim 130
Dependent Claim
52 words
The data processor of claim 96 wherein the second means also determines whether an operand must be transferred between said first processor and said evaluated effective address, and wherein the third means also indicate in said response that said transfer is required by said first processor in the execution of said instruction.
Claim 131
Dependent Claim
49 words
The data processor of claim 96 wherein the second means also determines a class of effective addresses valid for said instruction, and wherein the third means also indicate in said response that said effective address is to be evaluated only if said effective address is of said valid class.
Claim 132
Dependent Claim
35 words
The data processor of claim 98 further including: fourth means for receiving an error signal from said second processor indicating that said second processor determined that said effective address is not of said valid class.
Claim 133
Dependent Claim
52 words
The data processor of claim 98 wherein the second means also determines whether an operand must be transferred between said first processor and said evaluated effective address, and wherein the third means also indicate in said response that said transfer is required by said first processor in the execution of said instruction.
References Cited (Backward Citations)
No citation records indexed.
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