Multi-pipeline microprocessor with data precision mode indicator

Claim 2

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; and setting logic configured to set said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and to set said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units; wherein said multiple-precision instruction is a quad-precision instruction.

Claim 3

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; and stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicated by said precision mode indicator memory.

Claim 4

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; and stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicated by said precision mode indicator memory.

Claim 5

The microprocessor of claim 2 further comprising: setting logic configured to set said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and to set said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units.

Claim 6

The microprocessor of claim 3 wherein said multiple-precision instruction is a double-precision instruction.

Claim 7

The microprocessor of claim 2 further comprising a register file having a plurality of entries, each of said entries storing either a multiple precision operand or a plurality of single precision operands.

Claim 8

The microprocessor of claim 2 further comprising: a completion unit at the end of at least one of said functional units; and bypass logic configured to bypass said completion unit by using data from said first group of functional units without checking the precision of data being provided to said completion unit.

Claim 9

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; and a precision mode indicator memory associated with a first group of at least one of said functional units; wherein said dispatch unit further comprises: check logic configured to check data dependencies by comparing register designations of a new instruction to be dispatched to register designations of instructions in said first group of functional units, without considering whether said register designations are for single or multiple precision data.

Claim 10

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; and a precision mode indicator memory associated with a first group of at least one of said functional units; wherein said dispatch unit further comprises: check logic configured to check data dependencies by comparing register designations of a new instruction to be dispatched to register designations of instructions in said first group of functional units, without considering whether said register designations are for single or multiple precision data.

Claim 11

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; and a precision mode indicator memory associated with a first group of at least one of said functional units; wherein said precision mode indicator memory comprises a 2 bit register, a first bit indicating either single or double precision, and a second bit indicating that said first group of functional units is empty of active and valid instructions.

Claim 12

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; and a precision mode indicator memory associated with a first group of at least one of said functional units; wherein said precision mode indicator memory comprises a 2 bit register, a first bit indicating either single or double precision, and a second bit indicating that said first group of functional units is empty of active and valid instructions.

Claim 13

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; a second group of at least one of said functional units; and dependency logic configured to determine data dependencies for instructions to be dispatched to said second group of functional units by analyzing whether register designations overlap between single and multiple precision instructions.

Claim 14

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; a second group of at least one of said functional units; and dependency logic configured to determine data dependencies for instructions to be dispatched to said second group of functional units by analyzing whether register designations overlap between single and multiple precision instructions.

Claim 15

The microprocessor of claim 9 wherein said second group of functional units comprises a load and store functional unit.

Claim 16

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; setting logic configured to set said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and to set said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicated by said precision mode indicator memory; a register file having a plurality of entries, each of said entries storing either a multiple precision operand or a plurality of single precision operands; and check logic configured to check data dependencies by comparing register designations in said register file of a new instruction to be dispatched to register designations of instructions in said first group of functional units, without considering whether said register designations are for single or multiple precision data.

Claim 17

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; setting logic configured to set said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and to set said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicated by said precision mode indicator memory; a register file having a plurality of entries, each of said entries storing either a multiple precision operand or a plurality of single precision operands; and check logic configured to check data dependencies by comparing register designations in said register file of a new instruction to be dispatched to register designations of instructions in said first group of functional units, without considering whether said register designations are for single or multiple precision data.

Claim 18

The microprocessor of claim 11 wherein said precision mode indicator memory comprises a 2 bit register, a first bit indicating either single or double precision, and a second bit indicating that said first group of functional units is empty of active and valid instructions.

Claim 19

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; setting logic configured to set said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and to set said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicated by said precision mode indicator memory; a register file having a plurality of entries, each of said entries storing either a multiple precision operand or a plurality of single precision operands; check logic configured to check data dependencies by comparing register designations in said register file of a new instruction to be dispatched to register designations of instructions in said first group of functional units, without considering whether said register designations are for single or multiple precision data; a second group of at least one of said functional units; and dependency logic configured to determine data dependencies for instructions to be despatched to said second group of functional units by analyzing whether register designations overlap between single and multiple precision instructions.

Claim 20

A microprocessor comprising: a plurality of pipelined functional units configured to process instructions; a dispatch unit configured to dispatch instructions to said functional units; a precision mode indicator memory associated with a first group of at least one of said functional units; setting logic configured to set said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and to set said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicated by said precision mode indicator memory; a register file having a plurality of entries, each of said entries storing either a multiple precision operand or a plurality of single precision operands; check logic configured to check data dependencies by comparing register designations in said register file of a new instruction to be dispatched to register designations of instructions in said first group of functional units, without considering whether said register designations are for single or multiple precision data; a second group of at least one of said functional units; and dependency logic configured to determine data dependencies for instructions to be despatched to said second group of functional units by analyzing whether register designations overlap between single and multiple precision instructions.

Claim 23

The method of claim 14 further comprising the steps of: setting said precision mode indicator memory to a single-precision indication when a single precision instruction is dispatched to said first group of functional units and setting said precision mode indicator memory to a multiple-precision indication when a multiple-precision instruction is dispatched to said first group of functional units.

Claim 24

The method of claim 15 wherein said multiple-precision instruction is a double-precision instruction.

Claim 25

The method of claim 15 wherein said multiple-precision instruction is a quad-precision instruction.

Claim 28

A computer system comprising: a memory; a microprocessor coupled to said memory, said microprocessor including a plurality of pipelined functional units configured to process instructions, a dispatch unit configured to dispatch instructions to said functional units, a precision mode indicator memory associated with a first group of at least one of said functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; and stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicted by said precision mode indicator memory.

Claim 29

A computer system comprising: a memory; a microprocessor coupled to said memory, said microprocessor including a plurality of pipelined functional units configured to process instructions, a dispatch unit configured to dispatch instructions to said functional units, a precision mode indicator memory associated with a first group of at least one of said functional units; a comparator configured to compare a precision of a new instruction to be dispatched to a precision indicated by said precision mode indicator memory; and stalling logic configured to stall said new instruction when said new instruction has a precision which does not match the precision indicted by said precision mode indicator memory.