US5923893A
Expired / Lapsed
US
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Method and apparatus for interfacing a processor to a coprocessor
Assignee: NXP USA Inc
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Filing: 1997-09-05
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Granted: 1999-07-13
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Expires: 2017-09-05
Abstract
Abstract A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
Inventors
- 👤 William C. Moyer
- 👤 John Arends
- 👤 Jeffrey W. Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:37
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/3012; G06F9/38; G06F9/3861; G06F9/3877; G06F9/3879; G06F9/3881
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
154 words
A method for a processor to initiate, via a coprocessor bus, execution by a coprocessor of an instruction received by the processor for execution thereby, the method comprising the steps of: receiving said instruction; decoding said instruction; and providing to said coprocessor, at least partially coincident with said decoding: at least a predetermined portion of said instruction, via a first portion of said coprocessor bus, and a first control signal indicating that said instruction is being decoded by said processor via a second portion of said coprocessor bus; and wherein the method further comprising the steps of: transferring at least one information value between said processor and said coprocessor via said coprocessor bus; and if said at least one information value is being transferred from said processor to said coprocessor, providing a second control signal to said coprocessor bus to indicate that said at least one information value has been provided by said processor.
Claim 2
Independent Claim
154 words
A method for a processor to initiate, via a coprocessor bus, execution by a coprocessor of an instruction received by the processor for execution thereby, the method comprising the steps of: receiving said instruction; decoding said instruction; and providing to said coprocessor, at least partially coincident with said decoding: at least a predetermined portion of said instruction, via a first portion of said coprocessor bus, and a first control signal indicating that said instruction is being decoded by said processor via a second portion of said coprocessor bus; and wherein the method further comprising the steps of: transferring at least one information value between said processor and said coprocessor via said coprocessor bus; and if said at least one information value is being transferred from said processor to said coprocessor, providing a second control signal to said coprocessor bus to indicate that said at least one information value has been provided by said processor.
Claim 3
Dependent Claim
33 words
A method as in claim 1, further comprising the steps of: receiving a second control signal from said coprocessor bus; and if said second control signal is asserted, stalling execution of said instruction.
Claim 4
Dependent Claim
29 words
A method as in claim 1, further comprising the step of: providing a second control signal to said coprocessor bus to indicate when execution of said instruction is proceeding.
Claim 5
Dependent Claim
30 words
A method as in claim 3, further comprising the step of: if said first control signal is negated before said second control signal is asserted, discontinuing processing of said instruction.
Claim 6
Dependent Claim
58 words
A method as in claim 1, further comprising the steps of: if said at least one information value is being transferred from said coprocessor to said processor, providing said second control signal to said coprocessor bus to indicate that said at least one information value has been accepted by said processor and execution of said instruction may complete.
Claim 7
Dependent Claim
19 words
A method as in claim 5, wherein said at least one information value is a parameter of said instruction.
Claim 8
Dependent Claim
55 words
A method as in claim 1, further comprising the steps of: initiating a transfer of at least one information value between said processor and said coprocessor via said coprocessor bus; and providing a second control signal to said coprocessor bus to indicate that said transfer of said at least one information value has been unsuccessful.
Claim 9
Dependent Claim
44 words
A method as in claim 1, further comprising the step of: providing to said coprocessor, at least partially coincident with said step of decoding, at least a portion of a result produced by a previous instruction, via a third portion of said coprocessor bus.
Claim 10
Dependent Claim
30 words
A method as in claim 8, further comprising the step of: providing to said coprocessor, via said third portion of said coprocessor bus, a second result produced by said instruction.
Claim 11
Independent Claim
143 words
A method for a processor to initiate, via a coprocessor bus, execution by a coprocessor of an instruction received by the processor for execution thereby, the method comprising the steps of: in said processor: receiving said instruction; decoding said instruction; and providing to said coprocessor, at least partially coincident with said decoding, at least a predetermined portion of said instruction, via a first portion of said coprocessor bus, and a first control signal indicating that said instruction is being decoded by said processor via a second portion of said coprocessor bus; in said coprocessor: receiving from said processor, at least a predetermined portion of said instruction, via a first portion of said coprocessor bus, and a first control signal indicating that said instruction is being decoded by said processor, via a second portion of said coprocessor bus; and initiating execution of said instruction.
Claim 12
Independent Claim
143 words
A method for a processor to initiate, via a coprocessor bus, execution by a coprocessor of an instruction received by the processor for execution thereby, the method comprising the steps of: in said processor: receiving said instruction; decoding said instruction; and providing to said coprocessor, at least partially coincident with said decoding, at least a predetermined portion of said instruction, via a first portion of said coprocessor bus, and a first control signal indicating that said instruction is being decoded by said processor via a second portion of said coprocessor bus; in said coprocessor: receiving from said processor, at least a predetermined portion of said instruction, via a first portion of said coprocessor bus, and a first control signal indicating that said instruction is being decoded by said processor, via a second portion of said coprocessor bus; and initiating execution of said instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |