US4715013A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coprocessor instruction format
Assignee: NXP USA Inc
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Filing: 1986-07-25
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Granted: 1987-12-22
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Expires: 2006-07-25
Abstract
Abstract A system for interfacing a processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
Inventors
- 👤 Douglas B. MacGregor
- 👤 John Zolnowsky
- 👤 David Mothersole
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:34
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06F9/3881; G06F9/3861
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
242 words
In a data processing system responsive to a single stream of instructions, wherein the data processing system comprises: a general purpose processor adapted to independently decode and execute each of a first predetermined subset of said instructions; and any of a plurality of special purpose coprocessors each adapted to cooperate with the processor in the independent decoding and execution of each of a respective second predetermined subset of said instruction; the processor comprising: first means for receiving each of said instructions comprising said stream of instructions; second means for detecting in a predetermined operation bit field of each of said received instructions a predetermined bit value characteristic of each and every one of said instructions comprising said second subset of said instructions; third means for providing to said coprocessor from a predetermined command bit field of each of said detected instructions any of a plurality of predetermined command signal values each of which indicates a predetermined command which must be performed by said coprocessor in support of the execution of said detected instruction by the processor; fourth means for receiving from said coprocessor a response to the receipt of said command, said response comprising any of a plurality of response signal values each of which indicates whether a predetermined task must be performed by said processor in support of the performance of said command by said coprocessor; and fifth means for performing said task if indicated by said received response signal value.
Claim 2
Dependent Claim
242 words
In a data processing system responsive to a single stream of instructions, wherein the data processing system comprises: a general purpose processor adapted to independently decode and execute each of a first predetermined subset of said instructions; and any of a plurality of special purpose coprocessors each adapted to cooperate with the processor in the independent decoding and execution of each of a respective second predetermined subset of said instruction; the processor comprising: first means for receiving each of said instructions comprising said stream of instructions; second means for detecting in a predetermined operation bit field of each of said received instructions a predetermined bit value characteristic of each and every one of said instructions comprising said second subset of said instructions; third means for providing to said coprocessor from a predetermined command bit field of each of said detected instructions any of a plurality of predetermined command signal values each of which indicates a predetermined command which must be performed by said coprocessor in support of the execution of said detected instruction by the processor; fourth means for receiving from said coprocessor a response to the receipt of said command, said response comprising any of a plurality of response signal values each of which indicates whether a predetermined task must be performed by said processor in support of the performance of said command by said coprocessor; and fifth means for performing said task if indicated by said received response signal value.
Claim 3
Dependent Claim
217 words
In a data processing system responsive to a single stream of instructions, wherein the data processing system comprises: a general purpose processor adapted to independently decode and execute each of a first predetermined subset of said instructions; and any of a plurality of special purpose coprocessors each adapted to cooperate with the processor in the independent decoding and execution of each of a respective second predetermined subset of said instructions; the coprocessor comprising: first means for receiving from said processor from a predetermined command bit field of each of said instructions comprising the respective second subset of said instructions any of a plurality of predetermined command signal values each of which indicates a selected one of a plurality of predetermined commands which must be performed by said coprocessor in support of the execution of said instruction by the processor; second means for determining from said received command signal value whether a selected one of a plurality of predetermined tasks must be performed by said processor in support of the performance of said selected command by said coprocessor; and third means for providing to said processor a response having a predetermined response signal value which indicates that said selected task must be performed by said processor in support of the performance of said selected comand by said coprocessor.
Claim 4
Dependent Claim
217 words
In a data processing system responsive to a single stream of instructions, wherein the data processing system comprises: a general purpose processor adapted to independently decode and execute each of a first predetermined subset of said instructions; and any of a plurality of special purpose coprocessors each adapted to cooperate with the processor in the independent decoding and execution of each of a respective second predetermined subset of said instructions; the coprocessor comprising: first means for receiving from said processor from a predetermined command bit field of each of said instructions comprising the respective second subset of said instructions any of a plurality of predetermined command signal values each of which indicates a selected one of a plurality of predetermined commands which must be performed by said coprocessor in support of the execution of said instruction by the processor; second means for determining from said received command signal value whether a selected one of a plurality of predetermined tasks must be performed by said processor in support of the performance of said selected command by said coprocessor; and third means for providing to said processor a response having a predetermined response signal value which indicates that said selected task must be performed by said processor in support of the performance of said selected comand by said coprocessor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-21 | 1991-06-22 | 1991-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-21 | 1995-06-22 | 1995-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-21 | 1999-06-22 | 1999-12-22 | $7700.00 | Window Closed / Lapsed |