US5465376A
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Microprocessor, coprocessor and data processing system using them
Assignee: Renesas Electronics Corp
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Filing: 1993-05-05
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Granted: 1995-11-07
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Expires: 2013-05-05
Abstract
Abstract In a data processing system, the program counter (PC) values of coprocessor (CP) instructions are stored in a queue of a CP, and the stored PC value is not erased until the CP has completed executing the instruction. The need for a queue is caused by the pipeline in the CP. Three instructions may be executing concurrently and an exception may occur for any one of them. Accordingly, for example, at least 3 PC values must be stored in the queue. Early overwriting is prevented by making the queue 4 words deep. Also, the CP must assert a CPST signal before accepting a new command from the micro processor (MC). Thus, if the pipeline is full the CPST signal will not be asserted and the MP must wait before storing the new PC value in the queue. Instead of the entire PC, only an entry point is transferred to the CP. When only four PC values are saved, the entry point is only two bits and may be transferred along with the command information in a single bus cycle. If there are more than one CP, a program status word (PSW) includes a CPID for identifying which CP is to execute a received CP instruction. The queue and PCID system is only used for the first CP. In the event that an exception occurs, the entry point is transferred back to the MP and the PC of the instruction that took the exception is provided.
Inventors
- 👤 Toyohiko Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/34; G06F9/3818; G06F9/382; G06F9/3861; G06F9/3863; G06F9/3877
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
264 words
A processor system, comprising: an external memory; a first processor which executes first processor instructions; a second processor which is connected with said external memory via an external bus and with said first processor, and which executes second processor instructions, including: a decoder for decoding instructions, including said first and second processor instructions, fetched from said external memory via said external bus; and a program counter value calculator for calculating PC values of said first and second processor instructions, according to decoded results of said decoder; a first program counter which is connected with said program counter value calculator via a first internal signal path, and holds the PC values of said first processor instructions calculated by said program counter value calculator; and a second program counter which is connected with said program counter value calculator via a second internal signal path, and holds the PC value of said first and second processor instructions calculated by said program counter value calculator; wherein, when one first processor instruction is executed by said first processor, a PC value of said one first processor instruction is written into said first program counter from said program counter value calculator via said first internal signal path; and when an exception is generated by execution of said one first processor instruction in said first processor and a program for exception processing is activated, said PC value of said one first processor instruction is read out from said first program counter into said second processor via said first internal signal path by executing a predetermined instruction during execution of said program.
Claim 2
Dependent Claim
264 words
A processor system, comprising: an external memory; a first processor which executes first processor instructions; a second processor which is connected with said external memory via an external bus and with said first processor, and which executes second processor instructions, including: a decoder for decoding instructions, including said first and second processor instructions, fetched from said external memory via said external bus; and a program counter value calculator for calculating PC values of said first and second processor instructions, according to decoded results of said decoder; a first program counter which is connected with said program counter value calculator via a first internal signal path, and holds the PC values of said first processor instructions calculated by said program counter value calculator; and a second program counter which is connected with said program counter value calculator via a second internal signal path, and holds the PC value of said first and second processor instructions calculated by said program counter value calculator; wherein, when one first processor instruction is executed by said first processor, a PC value of said one first processor instruction is written into said first program counter from said program counter value calculator via said first internal signal path; and when an exception is generated by execution of said one first processor instruction in said first processor and a program for exception processing is activated, said PC value of said one first processor instruction is read out from said first program counter into said second processor via said first internal signal path by executing a predetermined instruction during execution of said program.
Claim 3
Dependent Claim
257 words
A processor system, comprising: an external memory; a floating-point processor which executes floating-point instructions; an integer processor which is connected with said external memory via an external bus and with said floating-point processor, and which executes integer instructions, including: a decoder for decoding instructions, including said integer instructions and floating-point instructions, fetched from said external memory via said external bus; and a program counter value calculator for calculating PC values of said integer instructions and floating-point instructions, according to decoded results of said decoder; a main program counter which is connected with said program counter value calculator via a first internal signal path, and holds the PC values of said integer instructions and floating-point instructions calculated by said program counter value calculator; and a floating-point program counter which is connected with said program counter value calculator via a second internal signal path, and holds the PC values of said floating-point instructions calculated by said program counter value calculator; wherein, when one floating-point instruction is executed by said floating-point processor, a PC value of said one floating-point instruction is written into said floating-point program counter from said program counter value calculator via said second internal signal path; and when an exception is generated by execution of said one floating-point instruction in said floating-point processor and a program for exception processing is activated, said PC value of said one floating-point instruction is read out from said floating-point program counter into said integer processor via said second internal signal path by executing a predetermined instruction during execution of said program.
Claim 4
Dependent Claim
257 words
A processor system, comprising: an external memory; a floating-point processor which executes floating-point instructions; an integer processor which is connected with said external memory via an external bus and with said floating-point processor, and which executes integer instructions, including: a decoder for decoding instructions, including said integer instructions and floating-point instructions, fetched from said external memory via said external bus; and a program counter value calculator for calculating PC values of said integer instructions and floating-point instructions, according to decoded results of said decoder; a main program counter which is connected with said program counter value calculator via a first internal signal path, and holds the PC values of said integer instructions and floating-point instructions calculated by said program counter value calculator; and a floating-point program counter which is connected with said program counter value calculator via a second internal signal path, and holds the PC values of said floating-point instructions calculated by said program counter value calculator; wherein, when one floating-point instruction is executed by said floating-point processor, a PC value of said one floating-point instruction is written into said floating-point program counter from said program counter value calculator via said second internal signal path; and when an exception is generated by execution of said one floating-point instruction in said floating-point processor and a program for exception processing is activated, said PC value of said one floating-point instruction is read out from said floating-point program counter into said integer processor via said second internal signal path by executing a predetermined instruction during execution of said program.
Claim 5
Dependent Claim
251 words
A processor system, comprising: an external memory; a coprocessor which executes coprocessor instructions; a main processor which is connected with said external memory via an external bus and with said coprocessor, and which executes main processor instructions, including: a decoder for decoding instructions, including said main and coprocessor instructions, fetched from said external memory via said external bus; and a program counter value calculator for calculating PC values of said main and coprocessor instructions, according to decoded results of said decoder; a first program counter which is connected with said program counter value calculator via a first internal signal path, and holds the PC values of said main and coprocessor instructions calculated by said program counter value calculator; and a second program counter which is connected with said program counter value calculator via a second internal signal path, and holds the PC values of said coprocessor instructions calculated by said program counter value calculator; wherein, when one coprocessor instruction is executed by said coprocessor, a PC value of said one coprocessor instruction is written into said second program counter from said program counter value calculator via said second internal signal path; and when an exception is generated by execution of said one coprocessor instruction in said coprocessor and a program for exception processing is activated, said PC value of said one coprocessor instruction is read out from said second program counter into said main processor via said second internal signal path by executing a predetermined instruction during execution of said program.
Claim 6
Dependent Claim
251 words
A processor system, comprising: an external memory; a coprocessor which executes coprocessor instructions; a main processor which is connected with said external memory via an external bus and with said coprocessor, and which executes main processor instructions, including: a decoder for decoding instructions, including said main and coprocessor instructions, fetched from said external memory via said external bus; and a program counter value calculator for calculating PC values of said main and coprocessor instructions, according to decoded results of said decoder; a first program counter which is connected with said program counter value calculator via a first internal signal path, and holds the PC values of said main and coprocessor instructions calculated by said program counter value calculator; and a second program counter which is connected with said program counter value calculator via a second internal signal path, and holds the PC values of said coprocessor instructions calculated by said program counter value calculator; wherein, when one coprocessor instruction is executed by said coprocessor, a PC value of said one coprocessor instruction is written into said second program counter from said program counter value calculator via said second internal signal path; and when an exception is generated by execution of said one coprocessor instruction in said coprocessor and a program for exception processing is activated, said PC value of said one coprocessor instruction is read out from said second program counter into said main processor via said second internal signal path by executing a predetermined instruction during execution of said program.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-11-06 | 1999-05-08 | 1999-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-06 | 2003-05-08 | 2003-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-06 | 2007-05-08 | 2007-11-07 | $7700.00 | Window Closed / Lapsed |