Communications base microcontroller

Claim 2

A communications base microcontroller for use in a multiplexing character processor of a type that interfaces a central processor to a multiplicity of peripheral devices controlled by program instructions from a multiplexing character processor communications program stored in an instruction memory, comprising: a scan list memory for storing a set of line addresses providing an order and a rate for multiplexing data and protocol information between each peripheral device and the central processor; said scan list memory outputting one of said line addresses in response to a corresponding signal of a plurality of timing signals; a direction list memory connected to the output of said scan list memory for storing a set of direction control bits for controlling a flow of the data and protocol information either in a direction for a peripheral device to central processor communication or a central processor to peripheral device communication, said direction list memory outputting one of said direction control bits in response to said scan list output and a second corresponding signal of said plurality of timing signals; program counter control means responsive to said scan list memory output, said direction list memory output and said timing signals for selecting one of a plurality of program counter registers for outputting a vector pointing to an address of a program instruction of said multiplexing character processor communications program to fetch said instruction from the instruction memory; an instruction execution means responsive to said scan list memory output, said direction list memory output, said pointing vector, and said timing signals for interpreting the fetched instruction, fetching data and operands from a data RAM, and executing the interpreted instruction, said instruction execution means including: program register means for receiving and storing said instruction fetched by said pointing vector; memory address register for storing an address for fetching data and operands from said data RAM; memory data register means for storing data and operands fetched from said data RAM; instruction interpretation means for decoding each instruction into at least one microsequence, each microsequence having at least one logical operation executeable in one machine cycle of the communication base microcontroller; execution means for fetching operands and data from said memory data register means and executing each microsequence in one machine cycle; and real time clock means for providing said timing signals to coordinate said scan list memory output, said direction list memory output, said program counter control means vector selection, and said instruction execution means.

Claim 3

A communications base microcontroller, according to claim 1, further comprising a single integrated circuit having said scan list memory, said direction list memory, program counter control means, said instruction execution device and said real time clock means as interconnected features thereof.

Claim 4

A communications base microcontroller for use in a multiplexing character processor of a type that interfaces a central processor to a multiplicity of peripheral devices controlled by program instructions from a multiplexing character processor communications program stored in an instruction memory, comprising: a scan list memory for storing a set of line addresses providing an order and a rate for multiplexing data and protocol information between each peripheral device and the central processor; said scan list memory outputting one of said line addresses in response to a corresponding signal of a plurality of timing signals; a direction list memory connected to the output of said scan list memory for storing a set of direction control bits for controlling a flow of the data and protocol information either in a direction for a peripheral device to central processor communication or a central processor to peripheral device communication, said direction list memory outputting one of said direction control bits in response to said scan list output and a second corresponding signal of said plurality of timing signals; program counter control means responsive to said scan list memory output, said direction list memory output and said timing signals for selecting one of a plurality of program counter registers for outputting a vector pointing to an address of a program instruction of said multiplexing character processor communications program to fetch said instruction from the instruction memory; an instruction execution means responsive to said scan list memory output, said direction list memory output, said pointing vector, and said timing signals for interpreting the fetched instruction, fetching data and operands from a data RAM, and executing the interpreted instruction, said instruction execution means including: program register means for receiving and storing said instruction fetched by said pointing vector; memory address register for storing an address for fetching data and operands from said data RAM; memory data register means for storing data and operands fetched from said data RAM; instruction interpretation means for decoding each instruction into at least one microsequence, each microsequence having at least one logical operation executeable in one machine cycle of the communication base microcontroller; execution means for fetching operands and data from said memory data register means and executing each microsequence in one machine cycle; and real time clock means for providing said timing signals to coordinate said scan list memory output, said direction list memory output, said program counter control means vector selection, and said instruction execution means at the preselected rate such that said instruction execution means appears to the peripheral devices and the central processor as a number of independent communications microcontrollers operating in parallel.

Claim 5

A communications base microcontroller for use in a multiplexing character processor of a type that interfaces a central processor to a multiplicity of peripheral devices controlled by program instructions from a multiplexing character processor communications program stored in an instruction memory, comprising: a scan list memory for storing a set of line addresses providing an order and a rate for multiplexing data and protocol information between each peripheral device and the central processor; said scan list memory outputting one of said line addresses in response to a corresponding signal of a plurality of timing signals; a direction list memory connected to the output of said scan list memory for storing a set of direction control bits for controlling a flow of the data and protocol information either in a direction for a peripheral device to central processor communication or a central processor to peripheral device communication, said direction list memory outputting one of said direction control bits in response to said scan list output and a second corresponding signal of said plurality of timing signals; program counter control means responsive to said scan list memory output, said direction list memory output and said timing signals for selecting one of a plurality of program counter registers for outputting a vector pointing to an address of a program instruction of said multiplexing character processor communications program to fetch said instruction from the instruction memory; an instruction execution means responsive to said scan list memory output, said direction list memory output, said pointing vector, and said timing signals for interpreting the fetched instruction, fetching data and operands from a data RAM, and executing the interpreted instruction, said instruction execution means including: program register means for receiving and storing said instruction fetched by said pointing vector; memory address register for storing an address for fetching data and operands from said data RAM; memory data register means for storing data and operands fetched from said data RAM; instruction interpretation means for decoding each instruction into at least one microsequence, each microsequence having at least one logical operation executeable in one machine cycle of the communication base microcontroller; execution means for fetching operands and data from said memory data register means and executing each microsequence in one machine cycle; and real time clock means for providing said timing signals to coordinate said scan list memory output, said direction list memory output, said program counter control means vector selection, and said instruction execution means at the preselected rate such that said instruction execution means appears to the peripheral devices and the central processor as a number of independent communications microcontrollers operating in parallel.