High-speed time share processor

Claim 1

A microcoded processor for use in a multi-channel high-speed data processing system in which each channel is processed in a time share mode by said processor according to selectable ones of a plurality of microcoded data handling routines, each channel having input and output signals, the processor comprising: (a) a sequence file, for storing addresses of the channels to be processed in which the stored addresses are outputted in response to a sequential sequence of storage location addresses, the outputted addresses controlling the order and rate at which each of the channels is time share processed according into which storage locations the address of each channel is stored in said sequence file, the processor processing each channel during time share intervals, and where the addresses in said sequence file may be changed during execution of the routines to provide for the dynamic control of the sampling of any given channel; (b) a program memory for storing the microcode instructions for the plurality of data handling routines, which routines process the various input and output signals of the channels; (c) a means of executing the microcode instructions stored in said program memory in which a predetermined number of microcode instructions are executed by said executing means for each channel during each time share interval; (d) a routine re-entry file having an addressable memory location associated with each channel, each re-entry file memory location storing the program memory address of the next program instruction to be executed during the next time share interval for its associated channel, the next instruction address stored for each channel controlling which of the plurality of data handling routines is next to be executed for the channel, the stored re-entry addresses independent of the routine being executed for the associated channel during its last time share interval; and (e) a channel data file having at least one block of memory locations associated with each channel, for storing and outputting to said executing means the data required by said executing means to process the next channel in a sequence, each associated block including memory locations for storing (1) constant data reqired by the data handling routines to process each channel, and (2) variable data required by the data handling routines to process each channel, where the function of each bit of each memory location for the variable data for each associated channel is variable and is redefined in accordance with which of the plurality of data handling routines is next to be executed for the associated channel; and (f) said executing means including a constant and a variable high-speed cache memory for respectively storing the constant and variable data required by the routine currently being executed, said constant and variable cache memories each comprising first and second cache memories each having active and inactive states such that, (1) when said first or second memory is in the active state, it contains the data for the current channel to be time share processed and is available for use by the microcode instructions, said active first or second variable cache memory adapted to permit the stored data to be modified during execution of the microcode instructions, and (2) when said first or second memories are in the inactive state it is available for storing the data for the next channel to be time share processed in the next time share interval, said first and second memories always in opposite states with their states switching at the completion of each time share interval.