Cache control for concurrent access

Claim 1

Means for controlling the overlapping of accessing of a cache during requests to the cache by a processor and by a storage entity transferring a line of data to the cache, each line being divided into a plurality of data groups, the cache having a single addressing means which sequentially receives addresses for all requests to the cache, comprising: means for timing request addresses to the cache during sub-cycles including: a first cache timing sub-cycle for timing each processor access request address to the addressing means, and a second cache timing sub-cycle for timing the address of each data group in a line being transferred to the cache, directory means operating within a sub-cycle for signalling whether a line of data for the processor request exists in the cache, the directory means indicating when the line does or does not exist in the cache, comparing means for receiving the line address for a line being fetched from the storage entity, the comparing means comparing the line address with each concurrent processor request address, first means for gating each requesting data group address to the cache during a second cache timing sub-cycle, and second means for gating each processor request address to the cache during a first cache timing sub-cycle when the directory indicates the processor request is in the cache and the comparing means indicates the processor request is for a different line in the cache than the line being fetched, whereby the transfer of a line from the storage entity to the cache proceeds without interruption while any concurrent processor request is accessing the cache.

Claim 7

A method of overlapping the accessing of a cache by a processor and by a storage entity transferring a line of data between the storage entity and the cache, the line including a plurality of data groups of bits in which each group is handled as a unit of data transfer, a cache address bus connecting the cache to the processor and to the storage entity to receive processor and storage access addresses, comprising the steps of: requesting a processor access to the cache during a processor machine cycle, providing at least two cache access timing sub-cycles during each processor machine cycle, a first cache timing sub-cycle timing the addressing of the cache by each processor request, a second cache timing sub-cycle timing the addressing of the cache by each data group in the line transfer, determining during the line transfer if a line of data exists in the cache for the processor request, and allowing on said buses on different sub-cycles, the tranfer of an address for a processor request if the determining step finds the line of data in the cache for the processor request, and the transfer of the address for a current data group in a line transfer, whereby a processor access to the cache is allowed during a line transfer to the cache.

Claim 8

A method of overlapping the accessing of a cache by a processor and by a storage entity transferring a line of data between the storage entity and the cache, the line including a plurality of data groups of bits in which each group is handled as a unit of data transfer, a cache address bus connecting the cache to the processor and to the storage entity to receive processor and storage access addresses, comprising the steps of: requesting a processor access to the cache during a processor machine cycle, providing at least two cache access timing sub-cycles during each processor machine cycle, a first cache timing sub-cycle timing the addressing of the cache by each processor request, a second cache timing sub-cycle timing the addressing of the cache by each data group in the line transfer, determining during the line transfer if a line of data exists in the cache for the processor request, and allowing on said buses on different sub-cycles, the tranfer of an address for a processor request if the determining step finds the line of data in the cache for the processor request, and the transfer of the address for a current data group in a line transfer, whereby a processor access to the cache is allowed during a line transfer to the cache.