Data processing system and method therefor

Claim 2

In a data processing system having a central processing unit (CPU), a main storage (MS) and a high-speed buffer storage (HSB) coupling said CPU to said MS, said MS being coupled to said HSB by parallel line connectIon means which will accommodate a predetermined plurality of bytes for data out of and into said MS, said HSB comprising: a plurality of primary storage units for storing said predetermined plurality of bytes, each of said storage units corresponding to a predetermined one of said bytes, gating means for bundling the data outputs of selected nonsequential pairs of said storage units, coupling means for separately coupling the data outputs of said selected nonsequential pairs of said storage units to said MS to move said predetermined plurality of bytes into said MS, means for enabling only one of said storage units of each of said pairs of said storage units at any one time, word register means (WR) for coupling said gating means to said CPU, said WR storing a number of bytes corresponding to the number of said nonsequential pairs, said number of bytes being a fraction of said predetermined plurality of bytes.

Claim 3

A system as in claim 1 where said gating means includes means for bundling said nonsequential pairs of said storage units so that said storage units in each of said pairs of said storage units are separated from each other by a number of other of said storage units equal to one less than said number of bytes.

Claim 4

A system as in claim 1 where said HSB includes a plurality of alternate storage units, where said coupling means includes means for bundling the data outputs of said alternate units with corresponding data outputs of said primary storage units and where said HSB includes means for enabling only one of said primary and alternate storage units at one time.

Claim 5

A system as in claim 3 where said bundling means includes DOT OR type gates.

Claim 6

A system as in claim 1 where said gating means for bundling includes DOT OR type gates.

Claim 7

A system as in claim 1 where the number of bytes of said word register is one-twelfth of said predetermined plurality of bytes.

Claim 8

A system as in claim 1 where said gating means include a plurality of selector means each associated with a predetermined byte of said word register means, each of said selector means having individual gates with all of said bundled pairs as respective inputs and having control inputs for selectively enabling a selected one of said individual gates in each of said plurality of selector means for coupling data carried on the bundled pair to said associated byte of said WR.

Claim 9

A system as in claim 7 including alignment control means responsive to an address input from said CPU to provide control signals for said control inputs for storing data in said WR in a predetermined alignment.

Claim 10

A system as in claim 8 where said control means includes means responsive to length and left/right justification instructions from said CPU for left/right justifying data in said WR.

Claim 11

A system as in claim 9 where each byte of said WR includes separate input gating means for data and for a parity bit and includes a plurality of parity bit generators, one corresponding to each byte of said WR, said generators responsive to a coincidence condition of said control signals and coupled to the control inputs of a corresponding selector means for storing a parity bit in said WR, said coincidence condition of said control signals occurring only when none of said individual gates of a selector means is enabled whereby the byte of said associated WR is blanked.

Claim 12

A system as in claim 10 including sign extension means for extending the sign of a byte stored in said WR when only the lower half of said WR is to be filled with data and the upper half is blanked, said sign extension means comprising: gating means responsive to an extend sign control signal, responsive to a signal for enabling the upper byte of said lower half of said WR and responsive to the highest-order bit of said upper byte for coupling said highest-order bit to said data input gates of said blanked bytes.

Claim 13

In a data processing system operating during timed system cycles, the apparatus comprIsing, a processing unit having first parallel line connection means for transferring in one system cycle a first predetermined number of bytes of data into or out from said processing unit, a main storage having second parallel line connection means for transferring in one system cycle a second predetermined number, not equal to said first predetermined number, of bytes of data into or out from said main storage, a buffer storage for coupling said processing unit to said main storage, said buffer storage including a number, equal to said second predetermined number, of first multi-bit, parallel-arrayed storage units; including selectable gating means for connecting said first storage units to said first parallel line connection means or to said second parallel line connection means; and including enabling means connected to said gating means for selecting bytes of data from a number, equal to said first predetermined number, of said first storage units for transfers between said processing unit and said buffer storage and for selecting bytes of data from a a number, equal to said second predetermined number, of said first storage units for transfers between said buffer storage and said main storage.

Claim 14

In a data processing system operating during timed system cycles, the apparatus comprIsing, a processing unit having first parallel line connection means for transferring in one system cycle a first predetermined number of bytes of data into or out from said processing unit, a main storage having second parallel line connection means for transferring in one system cycle a second predetermined number, not equal to said first predetermined number, of bytes of data into or out from said main storage, a buffer storage for coupling said processing unit to said main storage, said buffer storage including a number, equal to said second predetermined number, of first multi-bit, parallel-arrayed storage units; including selectable gating means for connecting said first storage units to said first parallel line connection means or to said second parallel line connection means; and including enabling means connected to said gating means for selecting bytes of data from a number, equal to said first predetermined number, of said first storage units for transfers between said processing unit and said buffer storage and for selecting bytes of data from a a number, equal to said second predetermined number, of said first storage units for transfers between said buffer storage and said main storage.

Claim 15

The apparatus of claim 12 wherein said second parallel line connection means includes means for transferring in one cycle said second predetermined number, greater than said first predetermined number, of bytes of data into or out from said main store.

Claim 16

The apparatus of claim 12 where said buffer storage includes a number, equal to said second predetermined number, of second multi-bit parallel-arrayed storage units; where said gating means includes means for bundling first data lines from said first storage units with corresponding second data lines from said second storage units; and where said enabling means includes means for selecting some of said first and second data lines.

Claim 17

In a data processing system operating during timed system cycles, the apparatus comprising, a processing unit having first parallel line connection means for transferring in one system cycle a first predetermined number of bytes of data into or out from said processing unit, main storage having second parallel line connection means for transferring in one system cycle a second predetermined number, not equal to said first predetermined number, of bytes of data into or out from said main storage, a buffer storage for coupling said processing unit to said main storage, said buffer storage including a number, equal to said second predetermined number of first storage units and of second storage units; including selectable gating means, said gating means having coupling means for bundling first data lines from said first storage units and for bundling second data lines from said second storage units, said gating means connecting said first or said second storage units to said first parallel line connection means or to said second parallel line connection means; and including enabling means connected to select said gating means for selecting bytes of data from a number, equal to said first predetermined number, of said first or said second storage units for transfers between said processing unit and said buffer storage and for selecting bytes of data from a number, equal to said second predetermined number, of said first or said second storage units for transfers between said buffer storage and said main storage.

Claim 18

In a data processing system operating during timed system cycles, the apparatus comprising, a processing unit having first parallel line connection means for transferring in one system cycle a first predetermined number of bytes of data into or out from said processing unit, main storage having second parallel line connection means for transferring in one system cycle a second predetermined number, not equal to said first predetermined number, of bytes of data into or out from said main storage, a buffer storage for coupling said processing unit to said main storage, said buffer storage including a number, equal to said second predetermined number of first storage units and of second storage units; including selectable gating means, said gating means having coupling means for bundling first data lines from said first storage units and for bundling second data lines from said second storage units, said gating means connecting said first or said second storage units to said first parallel line connection means or to said second parallel line connection means; and including enabling means connected to select said gating means for selecting bytes of data from a number, equal to said first predetermined number, of said first or said second storage units for transfers between said processing unit and said buffer storage and for selecting bytes of data from a number, equal to said second predetermined number, of said first or said second storage units for transfers between said buffer storage and said main storage.

Claim 19

The apparatus of claim 15 where said buffer storage includes accessing means for accessing said first number of bytes of data from said first storage units and from said second storage units for transfers between said processing unit and said buffer storage and for accessing said second number of bytes from said first storage units or from said second storage units for transfers between said main storage and said processing unit.

Claim 20

In a data processing system operating during timed system cycles and including a processing unit having firsT parallel line connection means, including a main store having second parallel line connection means, including a high-speed buffer having a predetermined number of multi-bit, parallel-arrayed storage units, including selectable gating means for connecting said storage units to said first or to said second parallel line connection means, the method comprising, enabling said gating means for a first system cycle to select bytes of data from said predetermined number of storage units, transferring in said first system cycle a first number, equal to said predetermined number, of bytes of data between said processing unit and said buffer through said gating means, enabling said gating means for a second system cycle to select bytes of data from a second number, not equal to said predetermined number, of said storage units, transferring in said second system cycle a number, equal to said second number, of bytes of data between said main store and said buffer through said gating means.

Claim 21

In a data processing system operating during timed system cycles and including a processing unit having firsT parallel line connection means, including a main store having second parallel line connection means, including a high-speed buffer having a predetermined number of multi-bit, parallel-arrayed storage units, including selectable gating means for connecting said storage units to said first or to said second parallel line connection means, the method comprising, enabling said gating means for a first system cycle to select bytes of data from said predetermined number of storage units, transferring in said first system cycle a first number, equal to said predetermined number, of bytes of data between said processing unit and said buffer through said gating means, enabling said gating means for a second system cycle to select bytes of data from a second number, not equal to said predetermined number, of said storage units, transferring in said second system cycle a number, equal to said second number, of bytes of data between said main store and said buffer through said gating means.