US3614747A
Expired / Lapsed
US
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Instruction buffer system
Assignee: Hitachi Ltd
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Filing: 1969-10-29
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Granted: 1971-10-19
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Expires: 1989-10-29
Abstract
Abstract An instruction buffer for electronic computer systems, mainly comprising a pair of groups of registers in which instructions read out from the memory unit are stored and a control unit for controlling the selection of said groups of registers, normally one group of registers being used and the second group being used when a conditional branch instruction occurs in the program, so as to store the instructions in the branch program, the subsequent use of the groups of registers depending on the fate of the branch condition, thereby the advanced control of readout being possible throughout the program, ensuring a high-speed operation.
Inventors
- 👤 Koichiro Ishihara
- 👤 Tetsunori Nishimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3808; G06F9/381
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
188 words
An instruction buffer system comprising a pair of symmetrical instruction storage means for storing instructions read out from a memory unit in a selected one of said pair of instruction storage means until said instructions are taken out to be executed at the central processor; buffer control means for normally designating a first one of said pair of storage means for storing an instruction read out from the memory unit, but designating the second one of said pair of storage means for storing an instruction at the address of branch read out from the memory unit when the central processor detects an instruction taken out from said first storage means to be a conditional branch instruction, said buffer control means selecting said second or first storage means respectively depending on whether the branch condition of said conditional branch instruction is fulfilled or not; means for successively writing instructions read out from the memory unit into the storage means selected under the control of said buffer control means; and readout means for taking out said instructions from said selected storage means to directly transfer them to the central processor.
Claim 2
Dependent Claim
188 words
An instruction buffer system comprising a pair of symmetrical instruction storage means for storing instructions read out from a memory unit in a selected one of said pair of instruction storage means until said instructions are taken out to be executed at the central processor; buffer control means for normally designating a first one of said pair of storage means for storing an instruction read out from the memory unit, but designating the second one of said pair of storage means for storing an instruction at the address of branch read out from the memory unit when the central processor detects an instruction taken out from said first storage means to be a conditional branch instruction, said buffer control means selecting said second or first storage means respectively depending on whether the branch condition of said conditional branch instruction is fulfilled or not; means for successively writing instructions read out from the memory unit into the storage means selected under the control of said buffer control means; and readout means for taking out said instructions from said selected storage means to directly transfer them to the central processor.
Claim 3
Dependent Claim
133 words
An instruction buffer system as defined in claim 1, wherein said buffer control means comprises a first indicating means for indicating that one of said instruction storage means in which the instructions to be transferred to the central proceSsor are stored; a second indicating means for normally indicating that one of said instruction storage means into which instructions read out from the memory are to be stored but indicating the other instruction storage means until the fate of the branch condition is decided whenever a conditional branch instruction is detected by the central processor; and means for invalidating the instructions stored in the one of the instruction storage means indicated by said first or second indicating means respectively depending on that the branch condition of said conditional branch instruction is fulfilled or not.
Claim 4
Dependent Claim
48 words
An instruction buffer system as defined in claim 2, wherein said first indicating means comprises a flip-flop circuit which reverses the outputs thereof each time when said flip-flop circuit receives from the central processor a signal indicating that the branch condition of said conditional branch instruction is fulfilled.
Claim 5
Dependent Claim
23 words
An instruction buffer system as defined in claim 1, wherein each of said pair of instruction storage means comprises a plurality of registers.
Claim 6
Dependent Claim
46 words
An instruction buffer system as defined in claim 4, wherein said means for writing instructions read out from the memory unit comprises means for designating that one of said registers in which the next instruction is to be written, and means for selecting said designated register.
Claim 7
Dependent Claim
50 words
An instruction buffer system as defined in claim 4, wherein said readout means comprises means for designating one of said registers in which instructions to be read out to the central processor are stored, and means for selecting said designated register in order to read out the instruction stored therein.
Claim 8
Dependent Claim
61 words
An instruction buffer system as defined in claim 4, wherein each of said registers comprises a part for storing an instruction, a reserve indicator part which indicates whether a signal requesting the instruction has been dispatched to the memory unit or not, and an occupation indicator part which indicates whether the requested instruction has been stored in said register or not.
Claim 9
Dependent Claim
78 words
An instruction buffer system as defined in claim 2, wherein said buffer control means includes loop control means which is controlled by a signal generated in the central processor and indicating the detection of a small loop by the central processor, so as to cause said pair of instruction storage means to function as a single continuous storage means to prevent instructions stored in said storage means from being invalidated while said small loop exists in the program.
Claim 10
Dependent Claim
74 words
An instruction buffer system as defined in claim 5, which further includes means for controlling the writing of an instruction read out from the memory unit to the instruction storage means according to an address signal of a register in the instruction storage means, said address signal being transferred to the memory unit along with a signal for requesting an instruction, and then returned along with the instruction read out from the memory unit.
Claim 11
Dependent Claim
58 words
An instruction buffer according to claim 2, wherein each of said pair of instruction storage means comprises a plurality of registers, said means for writing instructions read out from said memory unit comprises means for designating a specific one of said registers in which the next instruction is to be written, and means for selecting said designated register.
Claim 12
Dependent Claim
49 words
An instruction buffer in accordance with claim 10, wherein said readout means comprises means for designating one of said registers in which instructions to be read out to the central processor are stored, and means for selecting said designated register in order to read out the instruction stored therein.
Claim 13
Dependent Claim
56 words
An instruction buffer in accordance with claim 11, wherein each of said registers comprises a portion for storing an instruction, a reserve indicator portion for indicating whether a signal requesting the instruction has been dispatched to the memory unit and an occupation indicator portion which indicated whether the requested instructIon has been stored within said register.
Claim 14
Dependent Claim
72 words
An instruction buffer in accordance with claim 12, further including means for controlling the writing of an instruction read out from said memory unit in the instruction storage means in accordance with an address signal of a register in the instruction storage means, said address signal being transferred to said memory unit together with a signal for requesting an instruction, and being returned with the instruction read out from said memory unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |