US4016548A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Communication multiplexer module
Assignee: Unisys Corp
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Filing: 1975-04-11
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Granted: 1977-04-05
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Expires: 1995-04-11
Abstract
Abstract A communications multiplexer module (CMM) assembles serial by bit data from a plurality of input ports into parallel-by-bit characters before transmitting them to a host computer. On output operations the host computer supplies characters parallel-by-bit to the communications multiplexer module and the module dissassembles the characters into serial by bit data for distribution to output ports. The CMM includes a main memory for storing control words, there being one control word for each port. The main memory is scanned in a fixed sequence so that the control words are read out of the main memory in the same sequence that the input and output multiplexers for the ports are scanned. This permits most of the logic circuits of the CMM to be time shared between all ports the logic circuits being controlled in turn by each control word. Any port may be an input or an output port, the designation being determined by bits of the control word associated with the port. The control word also contains bits designating whether the port is to function in association with a synchronous or an asynchronous line adapter connected to the port, the number of bits in each character, and other information necessary for assembling input or disassembling output data and controlling the transfers between the ports and the computer. The control word has a character assembly/disassembly area where characters are assembled a bit at a time during input operations, and are disassembled a bit at a time during output operations. Characters are transferred between the assembly/disassembly area and the host computer through a storage area in the control word. Character detect tables are provided for sensing each input character after assembly, or each output character before disassembly and, if it is a control character, converting it into a standard control word code used within the CMM. The outputs from the character detect table control certain hard wired functions and, in addition, may address a second memory containing a plurality of control interpretation tables. In the character interpretation tables, each bit represents a specific function to be performed within the CMM. The control word associated with each port contains bits designating which character detect table and which control interpretation table is to be utilized with the port. This enables the CMM to recognize and respond to control functions in a uniform manner, even though the functions themselves may be represented by characters in different codes. Programmable procedure counters are provided for detecting various conditions such as a failure to detect an end character. Full error checking procedures are included in the CMM.
Inventors
- 👤 Wendell A. Law
- 👤 William G. Barrett
- 👤 Norman F. Priebe
- 👤 Harry D. Wise
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:32
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
391 words
In a communications multiplexer module for transferring data between a data processor and a plurality of line adapters, the combination comprising: an addressable memory including a plurality of addressable control word location, one location associated with each of said line adapters, each said control word location including means for storing signals representing a control word having a data character field, an end of character field, and an input/output field; scanning means for repetitively generating a sequence of addressing signals; means for applying said addressing signals to said memory to read out and then read back into each of said control word locations; multiplexer means connected to all said line adapters for receiving data therefrom one bit at a time; means for applying said addressing signals to said multiplexer means whereby a given line adapter is selected when the control word location associated with said given line adapter is addressed; time shared logic circuit means connected to said memory and said multiplexer means, said time shared logic circuit means including first circuit means responsive to a first combination of signals representing the input/output field of the control word presently addressed for gating a bit of data from said multiplexer means into the data character field of the control word presently addressed, as it is read back into its control word location; means in each line adapter producing a data clock signal which is applied to, and gated through said multiplexer means with each data bit; said time shared logic circuit means including second circuit means responsive to the data clock signal and the end of character field of the control word location being addressed to increment the end of character field, means for transmitting the incremented end of character field to said memory for storage when the addressed control word location is read back into; third circuit means in said time shared logic circuit means examining said end of character fields as they are read out of said memory and producing an end of character signal when the end of character field for an addressed control word location indicates that the number of bits of data entered into the data character field of the addressed control word location represents a complete data character; and means responsive to said end of character signal for transferring said complete data character to said data processor.
Claim 2
Dependent Claim
391 words
In a communications multiplexer module for transferring data between a data processor and a plurality of line adapters, the combination comprising: an addressable memory including a plurality of addressable control word location, one location associated with each of said line adapters, each said control word location including means for storing signals representing a control word having a data character field, an end of character field, and an input/output field; scanning means for repetitively generating a sequence of addressing signals; means for applying said addressing signals to said memory to read out and then read back into each of said control word locations; multiplexer means connected to all said line adapters for receiving data therefrom one bit at a time; means for applying said addressing signals to said multiplexer means whereby a given line adapter is selected when the control word location associated with said given line adapter is addressed; time shared logic circuit means connected to said memory and said multiplexer means, said time shared logic circuit means including first circuit means responsive to a first combination of signals representing the input/output field of the control word presently addressed for gating a bit of data from said multiplexer means into the data character field of the control word presently addressed, as it is read back into its control word location; means in each line adapter producing a data clock signal which is applied to, and gated through said multiplexer means with each data bit; said time shared logic circuit means including second circuit means responsive to the data clock signal and the end of character field of the control word location being addressed to increment the end of character field, means for transmitting the incremented end of character field to said memory for storage when the addressed control word location is read back into; third circuit means in said time shared logic circuit means examining said end of character fields as they are read out of said memory and producing an end of character signal when the end of character field for an addressed control word location indicates that the number of bits of data entered into the data character field of the addressed control word location represents a complete data character; and means responsive to said end of character signal for transferring said complete data character to said data processor.
Claim 3
Dependent Claim
60 words
The combination as claimed in claim 1 wherein each of said control word locations further includes means for storing signals representing a character length field of a control word, said character length field indicating the number of data bits in each character; and means for applying said character length fields to said means for examining said end of character fields.
Claim 4
Dependent Claim
443 words
In a communications multiplexer module for transferring data between a data processor and a plurality of line adapters, the combination comprising: an addressable memory including a plurality of addressable control word locations, one location associated with each said line adapters, each said control word location including means for storing signals representing a control word having a data character field, an end of character field, and an input/output field; scanning means for repetitively generating a sequence of address signals; means for applying said addressing signals to said memory to read out and then read back into each of said control word locations; multiplexer means connected to all said line adapters for receiving data therefrom, or transmitting data thereto, one bit at a time; means for applying said addressing signals to said multiplexer means whereby a given line adapter is selected when the control word location associated with said given line adapter is addressed; time shared logic circuit means connected to said memory and said multiplexer means, said time shared logic circuit means including first circuit means responsive to a first combination of signals representing the input/output field of the control word presently addressed for gating a bit of data from said multiplexer means into the data character field of the control word presently addressed, as it is read back into its control word location; means in each line adapter producing a data clock signal which is applied to, and gated through said multiplexer means with each data bit; said time shared logic circuit means including second circuit means responsive to the data clock signal and the end of character field control word location being addressed to increment the end of character field; means for transmitting the incremented end of character field to said memory for storage when the addressed control word location is read back into; third circuit means in said time shared logic circuit means examining said end of character fields as they are read out of said memory and producing an end of character signal when the end of character field for an addressed control word location indicates that the number of bits of data entered into the data character field of the addressed control word location represents a complete data character; and means responsive to said first combination of signals representing the input/output field and to said end of character signal for transferring a completed character from the data character field to the character storage field in the same control word location; and further means responsive to said end of character signal for transferring a data character from the character storage field of a control word location to said data processor.
Claim 5
Dependent Claim
443 words
In a communications multiplexer module for transferring data between a data processor and a plurality of line adapters, the combination comprising: an addressable memory including a plurality of addressable control word locations, one location associated with each said line adapters, each said control word location including means for storing signals representing a control word having a data character field, an end of character field, and an input/output field; scanning means for repetitively generating a sequence of address signals; means for applying said addressing signals to said memory to read out and then read back into each of said control word locations; multiplexer means connected to all said line adapters for receiving data therefrom, or transmitting data thereto, one bit at a time; means for applying said addressing signals to said multiplexer means whereby a given line adapter is selected when the control word location associated with said given line adapter is addressed; time shared logic circuit means connected to said memory and said multiplexer means, said time shared logic circuit means including first circuit means responsive to a first combination of signals representing the input/output field of the control word presently addressed for gating a bit of data from said multiplexer means into the data character field of the control word presently addressed, as it is read back into its control word location; means in each line adapter producing a data clock signal which is applied to, and gated through said multiplexer means with each data bit; said time shared logic circuit means including second circuit means responsive to the data clock signal and the end of character field control word location being addressed to increment the end of character field; means for transmitting the incremented end of character field to said memory for storage when the addressed control word location is read back into; third circuit means in said time shared logic circuit means examining said end of character fields as they are read out of said memory and producing an end of character signal when the end of character field for an addressed control word location indicates that the number of bits of data entered into the data character field of the addressed control word location represents a complete data character; and means responsive to said first combination of signals representing the input/output field and to said end of character signal for transferring a completed character from the data character field to the character storage field in the same control word location; and further means responsive to said end of character signal for transferring a data character from the character storage field of a control word location to said data processor.
Claim 6
Dependent Claim
101 words
The combination as claimed in claim 3 wherein any control word location may store a second combination of signals representing an input/output field of a control word; means for transferring data characters from said data processor to the data character fields of said control word locations; said time shared logic circuit means including means for transferring a bit of a character from one of said data character fields through said multiplexer means to the associated line adapter each time a control word location is addressed and the input/output field of the control word is represented by said second combination of signals.
Claim 7
Dependent Claim
102 words
The combination as claimed in claim 4 wherein said time shared logic circuit means includes means for incrementing the value from the end of character field each time the control word location containing the end of character field is addressed if the corresponding input/output field contains said second combination of bits; and means responsive to a predetermined value in any of said end of character fields of a control word location for transferring a new character to the data character field of the control word location if the input/output field in the same control word location contains said second combination of bits.
Claim 8
Dependent Claim
256 words
In a communications multiplexer module for transferring data between a data processor and a plurality of line adapters, the combination comprising: an addressable memory having a plurality of addressable control word locations, there being one location associated with each line adapter, and each location being capable of storing a control word including a data character field, a field designating input or output, and a preamble definition field, and multiplexer means for transferring bits of data read out of said memory to said line adapters, one bit at a time; means for loading said input/output field of predetermined ones of said control word locations from said data processor with signals designating an output operation; address generating means for supplying a sequence of addressing signals to said multiplexer means and said memory means to read out a control word location and select its associated line adapter; time shared logic circuit means connected to said addressable memory for operating in turn with each of said control words as its location is addressed; said time shared logic circuit means including means responsive to said addressable memory when a control word location is addressed, for utilizing said preamble definition field to generate a message preamble; said time shared logic circuit means including means for loading a generated preamble into the data character field of the control word which caused it to be addressed, and further including means for transferring one bit of said generated preamble to a line adapter each time the line adapter and its associated control word are addressed.
Claim 9
Dependent Claim
256 words
In a communications multiplexer module for transferring data between a data processor and a plurality of line adapters, the combination comprising: an addressable memory having a plurality of addressable control word locations, there being one location associated with each line adapter, and each location being capable of storing a control word including a data character field, a field designating input or output, and a preamble definition field, and multiplexer means for transferring bits of data read out of said memory to said line adapters, one bit at a time; means for loading said input/output field of predetermined ones of said control word locations from said data processor with signals designating an output operation; address generating means for supplying a sequence of addressing signals to said multiplexer means and said memory means to read out a control word location and select its associated line adapter; time shared logic circuit means connected to said addressable memory for operating in turn with each of said control words as its location is addressed; said time shared logic circuit means including means responsive to said addressable memory when a control word location is addressed, for utilizing said preamble definition field to generate a message preamble; said time shared logic circuit means including means for loading a generated preamble into the data character field of the control word which caused it to be addressed, and further including means for transferring one bit of said generated preamble to a line adapter each time the line adapter and its associated control word are addressed.
Claim 10
Dependent Claim
42 words
The combination as claimed in claim 6 wherein said generated preamble comprises more than one data character, said time shared logic circuit means including means for loading the characters of said preamble into the data character fields one character at a time.
Claim 11
Dependent Claim
107 words
The combination as claimed in claim 6 wherein each control word location further includes means for storing signals representing an end of character field, said means for loading characters including means for incrementing a value in an end of character field each time said memory is addressed and a bit of a preamble character is transferred from the data character field of the addressed location to the associated line adapter; and means responsive to a predetermined value read out of an end of character field for loading another preamble character into the data character field of the control word location from which said predetermined value was read.
Claim 12
Dependent Claim
84 words
The combination as claimed in claim 8 and wherein each control word location includes means for storing a confidence count field; said time shared logic circuit including means for incrementing the confidence count field of an addressed control word location each time a new preamble character is loaded into the data character field thereof, and means responsive to a predetermined value in a confidence count field for inhibiting further loading of preamble characters into the data character field of the associated control word location.
Claim 13
Dependent Claim
43 words
The combination as claimed in claim 9 wherein said time shared logic circuit means includes means responsive to said predetermined count in the confidence counter field for any control word for enabling the loading of a data character into said data character field.
References Cited (Backward Citations)
US3377619A
Cited
US3550133A
Cited
US3413612A
Cited
US3573740A
Cited
US3618031A
Cited
US3842405A
Cited
US3804987A
Cited
US3825905A
Cited
US3828325A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-04 | 1980-10-04 | 1981-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-04 | 1984-10-04 | 1985-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-04 | 1988-10-04 | 1989-04-05 | $7700.00 | Window Closed / Lapsed |