Binary synchronous communications processor system and method

Claim 2

In a communications processor system wherein a message switching digital computer is programmed to receive binary coded data from a remote terminal over a data buss and to transmit the coded data via the data buss to a communication station comprising: modem means for converting received binary coded tone signals into binary coded serial electrical signals, said electrical signals including text characters providing text data and control characters providing synchronization data, message block establishing data and error checking data, means connected with said modem means for converting said serial electrical signals received therefrom into parallel digital signals, a sync character detecting circuit responsive to one of said control characters providing synchronization data for generating a sync indication, lock circuitry responsive to said sync indication for establishing synchronization of said communications station with said parallel digital signals, a processor circuit coupled to the output of said converting means and including a LSI semiconductor device responsive to predetermined ones of said control characters providing message block establishing data for arranging said text data into message blocks having a predetermined number of text characters, a plurality of random access memories connected to said processor circuit for storing said message blockS while excluding said control characters, input buffer means connected between said memories and said data buss for receiving said message blocks under the control of said computer.

Claim 3

The combination of claim 1 and further comprising: cyclic redundancy check circuitry for computing an error check character for said stored message blocks and for comparing the computed error check character with the transmitted error checking character contained in said electrical signals.

Claim 4

The combination of claim 2 wherein said cyclic redundance check circuit comprises: means for determining the numeric binary value of a block of text data, dividing means for dividing the numeric binary value of a block of text data by a constant, means for discarding the quotient generated by said dividing means, and means for transmitting the remainder generated by said dividing means as said error check code.

Claim 5

The combination of claim 2 including means for transmitting said electrical binary coded signals in the transparent-text mode with additional characters being capable of utilization as data without taking on control meaning, said central processor unit including means for detecting said additional characters when preceded by a predetermined character for initiation of a control function.

Claim 6

The combination of claim 2 wherein said processor circuit comprises: means connected with said check circuitry for multiplexing said parallel digital signals with any output from said check circuitry resulting from said comparison therein, and means for directing the output of said multiplexing means to said memories.

Claim 7

The combination of claim 2 and further comprising: output buffer means connected to said high speed data buss for receiving parallel digital data from said computer, said buffer connected to said memories for storage of predetermined message blocks of said digital data under the control of said computer, said central processor unit operable to add line control and error checking characters to said digital data, and an output shift register connected between said memories and said modem means for transferring said digital data through said communications link to a remote station.

Claim 8

In a communication processor system including a message switching digital computer programmed to receive binary coded data from a plurality of communication stations connected to communication lines and to transmit said binary coded data to designated ones of said communication stations, the combination a first converter coupled to one of the communication lines for receiving serial digital data transmitted from one of said communication stations and for converting said received serial digital data into parallel digital data, said parallel digital data including control characters defining message blocks of a predetermined number of characters, a processor circuit responsive to said control characters for forming said parallel digital data into message blocks including said predetermined number of characters while stripping off said control characters from said data, means for storing said message blocks in a plurality of memories connected with said processor circuit, means for transmitting said message blocks to the computer, said processor circuit further including output means for receiving parallel digital data from the output of the computer and including means for adding control characters to said data in order to define the start and end of message blocks having a predetermined number of text characters, a second converter connected to the output of said processor circuit for converting said parallel digital data received from said computer into serial digital data for transmission to one of said communication lines, and means for transmitting said message blocks output from the computer and said added control characters through said second converter to one of said communication stations via said communication line.

Claim 9

In a communication processor system including a message switching digital computer programmed to receive binary coded data from a plurality of communication stations connected to communication lines and to transmit said binary coded data to designated ones of said communication stations, the combination a first converter coupled to one of the communication lines for receiving serial digital data transmitted from one of said communication stations and for converting said received serial digital data into parallel digital data, said parallel digital data including control characters defining message blocks of a predetermined number of characters, a processor circuit responsive to said control characters for forming said parallel digital data into message blocks including said predetermined number of characters while stripping off said control characters from said data, means for storing said message blocks in a plurality of memories connected with said processor circuit, means for transmitting said message blocks to the computer, said processor circuit further including output means for receiving parallel digital data from the output of the computer and including means for adding control characters to said data in order to define the start and end of message blocks having a predetermined number of text characters, a second converter connected to the output of said processor circuit for converting said parallel digital data received from said computer into serial digital data for transmission to one of said communication lines, and means for transmitting said message blocks output from the computer and said added control characters through said second converter to one of said communication stations via said communication line.

Claim 10

The combination of claim 7 and further comprising: error checking means connected within said processor circuit for checking the accuracy of said stored message blocks prior to transmission of said message blocks to said computer.

Claim 11

The combination of claim 8 wherein said error checking means comprises a cyclic redundancy check circuit for computing an error check code from said message blocks and including means for comparing the computed error check code with an error check code originally transmitted with said digital data.

Claim 12

The combination of claim 7 and further comprising: means for converting series digital tone data on said communication line into series electrical digital data for conversion by said first converter.

Claim 13

The combination of claim 7 wherein said processor circuit comprises: a central processor unit, a plurality of read only memories connected to said processor unit for storing instructions for said central processor unit, and a plurality of random access memories for storing said message blocks prior to transmission to the computer.