Microprocessor system

Claim 2

A microprocessor system comprising: a bus; a coprocessor coupled to said bus; and a master processor coupled to said bus for executing a bus access cycle for said coprocessor; and an external device coupled to said bus, said coprocessor including first judge means for judging a completion of a sequence of data transfer operations effected between an internal section of said coprocessor and said external device with respect thereto; and said master processor including second judge means for judging a completion of said sequence of data transfer operations independently of said first judge means, wherein said second judge means effects said judging of the completion of said sequence of data transfer operations, in said second judging means, based on a count of said data transfer operations, wherein said first judge means and said second judge means each are find first set bit circuits respectively disposed in said coprocessor and said master processor, each said find first set bit circuit including means for effecting for each data transfer operation a code inversion on a predetermined code bit included in a plurality of bit sets of data transferred in said each data transfer operation, which bit sets are applied to each said find first set bit circuit so as to update said data of said plurality of bit sets, and means for effecting a judgement of a completion of operations for said each data transfer operation based on a condition that said updated data transferred in said each data transfer operation does not include said predetermined code bit.

Claim 3

A microprocessor system according to claim 1, wherein said data of said plurality of bit sets of data transferred in said each data transfer operation designates, based on a combination of each bit code, a predetermined one of a plurality of internal data storage means possessed by said coprocessor.

Claim 4

A microprocessor system according to claim 2, wherein each of said find first set bit circuits includes means for deciding data of a plurality of bit sets thereto for controlling a designation of said internal data storage means of said coprocessor.

Claim 5

A microprocessor system according to claim 3, wherein said data of said plurality of bit sets of data transferred in said each data transfer operation is contained in an instruction to be fetched by said master processor for said coprocessor.

Claim 6

A microprocessor system according to claim 4, wherein said master processor includes means for slicing an instruction to be fetched from said master processor for said coprocessor and for generating a command for said coprocessor, said command containing said data of said plurality of bit sets of data transferred in said each data transfer operation.

Claim 7

A microprocessor system according to claim 2, wherein said plurality of internal data storage means include a plurality of general-purpose registers.

Claim 8

A microprocessor system according to claim 1, wherein said internal section includes a plurality of data storage means for storing data and wherein said plurality of bit sets designate a predetermined one of said plurality of data storage means.

Claim 9

A microprocessor system according to claim 7, wherein each of said find first set bit circuits includes means for deciding said plurality of bit sets to designate one of said data storage means of said coprocessor.

Claim 10

A microprocessor system according to claim 8, wherein said plurality of bit sets is included in an instruction to be fetched by said master processor for said coprocessor.

Claim 11

A microprocessor system according to claim 9, wherein said master processor includes means for forming a command to be provided to said coprocessor, on the basis of said instruction fetched by said master processor, said command including a plurality of bit sets to be set into the find first set bit circuit of said coprocessor.

Claim 12

A microprocessor system according to claim 7, wherein said plurality of data storage means include a plurality of general-purpose registers.

Claim 13

In a microprocessor which includes steps for an operation effected by a coprocessor coupled to a bus to communicate a sequence of plural data between an external device coupled to said bus and a plurality of data storage means included in said coprocessor according to a bus access cycle activated by a master processor coupled to said bus, said steps including: a fetch step to be used by said master processor to fetch a predetermined instruction from said master processor for said coprocessor; a command step following said fetch step to be used by said master processor to generate a command for said coprocessor based on said instruction fetched in said fetch step; and a step following said command step to be used by said master processor to supply said command generated in said command step to said coprocessor, wherein said master processor further includes means of effecting a step for monitoring an end of a sequence of data transfer operations based on data contained in said instruction, and wherein said coprocessor includes means for effecting a step for monitoring an end of a sequence of data transfer operations based on said information contained in said command independently of said monitoring step carried out by said master processor, and a step operative based on said data contained in said command for judging and for designating for each data transfer cycle a data storage position used as a data transfer source or destination in said coprocessor, wherein said step for judging and for designating for each data transfer cycle a data storage position comprises: effecting for each data transfer operation a code inversion on a predetermined code bit included in a plurality of bit sets of data transferred in said each data transfer operation; and effecting a judgment of a completion of operations for said each data transfer operation based on a condition that said updated data transferred in said each data transfer operation does not include said predetermined code bit.

Claim 14

In a microprocessor which includes steps for an operation effected by a coprocessor coupled to a bus to communicate a sequence of plural data between an external device coupled to said bus and a plurality of data storage means included in said coprocessor according to a bus access cycle activated by a master processor coupled to said bus, said steps including: a fetch step to be used by said master processor to fetch a predetermined instruction from said master processor for said coprocessor; a command step following said fetch step to be used by said master processor to generate a command for said coprocessor based on said instruction fetched in said fetch step; and a step following said command step to be used by said master processor to supply said command generated in said command step to said coprocessor, wherein said master processor further includes means of effecting a step for monitoring an end of a sequence of data transfer operations based on data contained in said instruction, and wherein said coprocessor includes means for effecting a step for monitoring an end of a sequence of data transfer operations based on said information contained in said command independently of said monitoring step carried out by said master processor, and a step operative based on said data contained in said command for judging and for designating for each data transfer cycle a data storage position used as a data transfer source or destination in said coprocessor, wherein said step for judging and for designating for each data transfer cycle a data storage position comprises: effecting for each data transfer operation a code inversion on a predetermined code bit included in a plurality of bit sets of data transferred in said each data transfer operation; and effecting a judgment of a completion of operations for said each data transfer operation based on a condition that said updated data transferred in said each data transfer operation does not include said predetermined code bit.

Claim 15

A microprocessor according to claim 12, wherein said data of the plurality of bit sets of data transferred in said each data transfer operation designates, based on a combination of each bit code, a predetermined one of a plurality of internal data storage means possessed by said coprocessor.

Claim 16

In a microprocessor system which includes a bus, a master processor coupled to said bus, a coprocessor coupled to said bus and an external device coupled to said bus, a method for executing a sequence of data transfer operations between said external device and a plurality of data storage means included in said coprocessor according to bus access cycles activated by said master processor, via said bus, said method comprising the steps including: (a) fetching a predetermined instruction from said coprocessor, by said master processor; (b) generating a command for said coprocessor based on said instruction fetched in said fetch step (a), by said master processor; and (c) providing said command generated in said command step to said coprocessor, wherein said master processor includes means for effecting a step for monitoring an end of said sequence of said data transfer operations based on data included in said instruction, and wherein said coprocessor includes means for effecting a step for monitoring an end of said sequence of said data transfer operation based on data included in said command independently of the monitoring carried out by said master processor.

Claim 17

In a microprocessor system which includes a bus, a master processor coupled to said bus, a coprocessor coupled to said bus and an external device coupled to said bus, a method for executing a sequence of data transfer operations between said external device and a plurality of data storage means included in said coprocessor according to bus access cycles activated by said master processor, via said bus, said method comprising the steps including: (a) fetching a predetermined instruction from said coprocessor, by said master processor; (b) generating a command for said coprocessor based on said instruction fetched in said fetch step (a), by said master processor; and (c) providing said command generated in said command step to said coprocessor, wherein said master processor includes means for effecting a step for monitoring an end of said sequence of said data transfer operations based on data included in said instruction, and wherein said coprocessor includes means for effecting a step for monitoring an end of said sequence of said data transfer operation based on data included in said command independently of the monitoring carried out by said master processor.

Claim 18

A method according to claim 14, wherein the monitoring to be effected by said master processor includes a step for stopping an activation of a further bus access cycle after a detection of said end of the sequence of data transfer operations.

Claim 19

A method according to claim 15, wherein said monitoring by said coprocessor includes a step for stopping an input or output operation of data after a detection of said end of said sequence of data transfer operations.

Claim 20

A method according to claim 14, wherein the monitoring by said coprocessor includes a step for stopping an activation of a further bus access cycle after a detection of said end of said sequence of data transfer operations.

Claim 21

A method according to claim 14, further including a step operative based on said data included in said command for judging and for designating, for each data transfer cycle, data storage means used as a data transfer source or destination in said coprocessor.

Claim 22

A method according to claim 18, wherein said step for judging and for designating for each data transfer cycle the data storage means comprises: effecting for each data transfer operation a code inversion on a predetermined code bit included in said data; and effecting a judgment of a completion of operations for said each data transfer operation based on a condition that said data do not include said predetermined code bit.

Claim 23

A method according to claim 19, wherein the plurality of bits included in said data indicate, based on a combination of each bit code, a predetermined one of the data storage means included in said coprocessor.

Claim 24

A microprocessor system comprising: a bus; a coprocessor coupled to said bus; a master processor coupled to said bus for executing a bus access cycle for said coprocessor; and an external device coupled to said bus, wherein said coprocessor includes a first find set bit means for judging a completion of a sequence of data transfer operations effected between a plurality of internal sections of said coprocessor and said external device, wherein said master processor includes second find first set bit means for judging a completion of said sequence of data transfer operations, and wherein each of said first and second find first set bit means includes means in which is set a plurality of information bits for indicating said internal sections, means for updating said set information bits in response to each of said data transfer operations and means for judging the updated information bits to determine whether or not each of said updated set information bits reaches a predetermined state.

Claim 25

A microprocessor system comprising: a bus; a coprocessor coupled to said bus; a master processor coupled to said bus for executing a bus access cycle for said coprocessor; and an external device coupled to said bus, wherein said coprocessor includes a first find set bit means for judging a completion of a sequence of data transfer operations effected between a plurality of internal sections of said coprocessor and said external device, wherein said master processor includes second find first set bit means for judging a completion of said sequence of data transfer operations, and wherein each of said first and second find first set bit means includes means in which is set a plurality of information bits for indicating said internal sections, means for updating said set information bits in response to each of said data transfer operations and means for judging the updated information bits to determine whether or not each of said updated set information bits reaches a predetermined state.

Claim 26

A microprocessor system according to claim 21, wherein said internal sections include a plurality of registers.

Claim 27

A microprocessor system according to claim 22, wherein said updating means includes inversion means for inverting a predetermined information bit of said set information bits in response to one of said data transfer operations.

Claim 28

A microprocessor system according to claim 23, wherein said predetermined information bit is a bit for indicating a register, to be transferred with data among said register, in response to said one data transfer operation.

Claim 31

A method according to claim 25, wherein said internal sections includes a plurality of registers.

Claim 32

A method according to claim 26, wherein said updating step (c) includes a step (c1) for inverting a predetermined bit in the set first information bits in response to one of said data transfer operations in said master processor.

Claim 33

A method according to claim 27, wherein said updating step (d) includes a step (d1) for inverting a predetermined bit in the set second information bits in response to one of said data transfer operations in said coprocessor.

Claim 34

A microcomputer system comprising: a bus; a coprocessor coupled to said bus; a master processor coupled to said bus for executing a bus access cycle for said coprocessor; and an external device coupled to said bus; said master processor including: transfer means for transferring a command to the coprocessor, calculation means for executing a calculation of an address of the external device for a data transfer operation, and first set means set with a data transfer number between the coprocessor and the external device included in the command, wherein the master processor includes means for judging completion of the data transfer operation independently of the coprocessor in accordance with the set data transfer number of the first set means, said coprocessor including: second set means set with the data transfer number included in the command provided from the master processor, wherein the coprocessor includes means for judging completion of the data transfer operation effected between an internal section of the coprocessor and the external device in accordance with the set data transfer number of the second set means, wherein the data transfer operation between the coprocessor and the external device is executed through the bus without passing through the master processor.

Claim 35

A microcomputer system comprising: a bus; a coprocessor coupled to said bus; a master processor coupled to said bus for executing a bus access cycle for said coprocessor; and an external device coupled to said bus; said master processor including: transfer means for transferring a command to the coprocessor, calculation means for executing a calculation of an address of the external device for a data transfer operation, and first set means set with a data transfer number between the coprocessor and the external device included in the command, wherein the master processor includes means for judging completion of the data transfer operation independently of the coprocessor in accordance with the set data transfer number of the first set means, said coprocessor including: second set means set with the data transfer number included in the command provided from the master processor, wherein the coprocessor includes means for judging completion of the data transfer operation effected between an internal section of the coprocessor and the external device in accordance with the set data transfer number of the second set means, wherein the data transfer operation between the coprocessor and the external device is executed through the bus without passing through the master processor.

Claim 36

A microprocessor system according to claim 29, wherein each of the first and second set means is a find first set bit circuit, and wherein said find first set bit circuit includes means for effecting for each data transfer operation a code inversion on a predetermined code bit included in a plurality of bit sets which have been set to the find first set bit circuit so as to update the plurality of bit sets, and means for effecting a judgment of a completion of the sequence of the data transfer operations based on a condition that each of the updated bit sets does not include the predetermined code bit.

Claim 37

A microprocessor system according to claim 30, wherein the internal section of the coprocessor includes a plurality of data storage means for storing data, and wherein the plurality of bit sets designate a predetermined one of the plurality of data storage means.

Claim 38

A microprocessor system according to claim 31, wherein each of the find first set bit circuits includes means for decoding the plurality of bit sets to designate one of the data storage means of the coprocessor.

Claim 39

A microprocessor system according to claim 32, wherein the master processor includes means for forming the command to be provided to the coprocessor, on the basis of the instruction fetched by the master processor, the command including a plurality of bit sets to be set into the find first set bit circuit of the coprocessor.

Claim 40

A microprocessor system according to claim 33, wherein the plurality of data storage means includes a plurality of general purpose registers.

Claim 41

A microprocessor system according to claim 34, wherein the external device is memory means for data.