EP0139254A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Apparatus and method for direct memory to peripheral and peripheral to memory data transfer
Assignee: International Business Machines Corp
•
Filing: 1984-09-28
•
Granted: —
•
Expires: 2004-09-28
Abstract
Abstract 57 A multi-microprocessor implemented data processing system (10) having a single cycle data transfer capability for its memory mapped peripheral devices (16) is described. A host of controlling microprocessor (12, 14) provides address and control signals for memory (24) accesses. In addition, it also determines that a peripheral (16) operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means (28) are provided to detect the special decode and to intercept the data bus (22) at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral (16) to enable the desired data transfer after the data bus has been intercepted.
Inventors
- 👤 Joseph P. Buonomo
- 👤 Raymond E. Losinger
- 👤 Burton L. Oliver
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 10:24
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
246 words
l. Apparatus (28) for effecting data transfer to and from a selected one of a plurality of memory mapped peripheral devices in a microprocessor implemented data processing system (10) having main storage means (24), control storage means (26) and a system bus (18, 22) to which said microprocessor (12, 14), peripheral devices (16) and storage means are connected, said apparatus being characterized by: a) a plurality of locations (30) in said control storage means (26), each having a unique address associated therewith, one each of said locations being mapped to a different one of said plurality of peripheral devices (16); b) first control logic means (40, 42, 44, 50, 54), connected between said plurality of peripheral devices and said plurality of memory mapped control storage locations, for detecting an access to any one of said memory mapped locations and for generating an initiate peripheral operation signal (46) in response thereto that will ready said peripheral (16) for operation upon receipt thereof; c) second control logic means (62, 68, 78, 86, 96, 108, 118, 130), associated with said microprocessor, for placing a peripheral (16) authorizing signal (80, 120) on the output thereof whenever said microprocessor (12) does a memory (24) access on behalf of a readied peripheral; and d) third control logic means (90, 92, 124), connected to and between said microprocessor, said accessed peripheral device and said system bus, for granting system bus control to a readied peripheral in response to an authorizing signal (120) therefor.
Claim 2
Dependent Claim
45 words
The apparatus according to claim 1 wherein said second control logic means includes circuit means (56) for toggling said authorizing signal (46) between logical off and on as a function of the condition of a predetermined address bit in the address of an accessed peripheral.
Claim 3
Dependent Claim
67 words
The apparatus according to claim 1 or 2 which further comprises data buffering means (90, 92) having bidirectional data flow and a switchable input (124) which controls the direction of data flow therethrough, connected between said peripherals (16) and said system bus (22), for switching the direction of data flow to and from an accessed peripheral in accordance with a signal applied to said switchable input thereof.
Claim 4
Independent Claim
35 words
The apparatus according to a previous claim wherein said second control logic means further includes means (64, 102) for differentiating the type of memory access to be made and for conditioning said accessed peripheral accordingly.
Claim 5
Independent Claim
210 words
A method of effecting data transfer to and from a selected one (16) of a plurality of memory mapped peripheral devices in a microprocessor implemented data processing system (10) having main storage means (24), control storage means (26) and a system bus (18, 22) to which said microprocessor (12, 14), peripheral devices (16) and storage means are connected, said method being characterized by the steps of: a) providing address and control signals from said microprocessor (12) for access of said main storage (24) and said memory mapped storage locations (30); b) monitoring (50) said memory mapped locations to determine when and which peripheral is being accessed; c) generating (50) a signal indicative of an access to a particular memory mapped location as a result of monitoring said location; d) sending (40, 42, 44, 54) a command signal (46) to said accessed peripheral (16) in response thereto; e) initiating (38) a memory cycle after access of said memory mapped location and sending of said command signal and generating a special memory access signal (72, 110) indicative thereof; and f) intercepting (68, 62, 78, 80, 82, 96, 118, 120, 122, 124) the system bus (22) at an appropriate time in reponse to the presence of said special memory access signal (72, 110).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.