US4598356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system including a main processor and a co-processor and co-processor error handling logic
Assignee: International Business Machines Corp
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Filing: 1983-12-30
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Granted: 1986-07-01
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Expires: 2003-12-30
Abstract
Abstract In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction.
Inventors
- 👤 Mark E. Dean
- 👤 Dennis L. Moeller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:07
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0745; G06F11/0721; G06F11/0724; G06F11/0793; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
148 words
A data processing sysem comprising a main processor, a co-processor having a busy output which, when active, indicates that the co-processor is executing a command and is not available for external data transfer, and an error output which, when active, indicates a co-processor malfunction, and a logic circuit having inputs coupled respectively ot the error and busy outputs of the co-processor and including first logic means responsive only to coincident active error and busy outputs to generate an interrupt request signal to initiate a main processor error interrupt routine, second logic means responsive to an active busy signal from the co-processor to provide an active busy signal to the main processor, and latching means responsive to the interrupt request signal to latch the active busy signal to the main processor to prevent the main processor from executing a co-processor instruction until the interrupt is handled by said routine.
Claim 2
Dependent Claim
148 words
A data processing sysem comprising a main processor, a co-processor having a busy output which, when active, indicates that the co-processor is executing a command and is not available for external data transfer, and an error output which, when active, indicates a co-processor malfunction, and a logic circuit having inputs coupled respectively ot the error and busy outputs of the co-processor and including first logic means responsive only to coincident active error and busy outputs to generate an interrupt request signal to initiate a main processor error interrupt routine, second logic means responsive to an active busy signal from the co-processor to provide an active busy signal to the main processor, and latching means responsive to the interrupt request signal to latch the active busy signal to the main processor to prevent the main processor from executing a co-processor instruction until the interrupt is handled by said routine.
Claim 3
Dependent Claim
37 words
A data processing system according to claim 1 in which the logic circuit includes third logic means responsive to a clear busy command from the main processor to clear the active busy signal to an inactive state.
Claim 4
Dependent Claim
59 words
A data processing system according to claim 2 including an interrupt control unit having a plurality of interrupt request inputs and an interrupt output coupled to the main processor to signal an interrupt operation by the main processor in response to an interrupt request signal from the logic circuit coupled to a predetermined one of the interrupt request inputs.
Claim 5
Dependent Claim
53 words
A data processing system according to claim 3 in which the logic circuit includes fourth logic means responsive to signals representing an I/O write command from the main processor defining the co-processor to generate an active chip select signal to the co-processor to enable data transfer from the co-processor to the main processor.
Claim 6
Dependent Claim
42 words
A data processing system according to claim 3 in which the logic circuit includes fourth logic means responsive to signals representing a co-processor reset command from the main processor to generate a reset signal to reset the co-processor to a dormant state.
References Cited (Backward Citations)
US3864670A
Cited
US3786430A
Cited
US3771131A
Cited
US3866184A
Cited
US3882455A
Cited
US4253183A
Cited
US4392201A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-30 | 1989-12-30 | 1990-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-30 | 1993-12-30 | 1994-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-30 | 1997-12-30 | 1998-07-01 | $7700.00 | Window Closed / Lapsed |