EP0021365A2
Expired / Lapsed
EP
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Data processing system with a slave computer
Assignee: Toshiba Corp
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Filing: 1980-06-20
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Granted: —
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Expires: 2000-06-20
Abstract
Abstract In a data processing system having a slave computer connecting to a host central processing unit (31) and a host main memory (35), the slave computer includes an arithmetic logic operating means (25). The arithmetic logic operating means (25) calculates an address of the host main memory (35). A DMA interface (23) directly makes an access to the host main memory (35) to fetch operand data into the slave computer. The arithmetic logic operating means (25) computes the operand data under control of a microprogram control section (27) and directly loads the computed result to the host main memory (35) through the DMA interface (23).
Inventors
- 👤 Shigeki Shibayama
- 👤 Kazuhide Iwata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:51
CPC Classifications
G; G06; G06T; G06T12/00; G06T12/20; G06F; G06F15/00; G06F15/16; G06F15/161; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06T2211/00; G06T2211/40; G06T2211/428
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
189 words
In a data processing system with a slave computer connecting to a host central processing unit and a host main memory, the improvement wherein said slave computer comprising: arithmetic logic operating means of which the operation cycle time is shorter than the memory cycle time of said host main memory, and computes the address of the host main memory; DMA interface means which is connected to said host main memory and said arithmetic logic operating means, directly makes an access to said host main memory by the address computed by said arithmetic logic operating means, and directly loads the result of said arithmetic logic operating means to said host main memory; microprogram control means connected to said arithmetic logic operating means and said DMA interface means for controlling those means; input/output interface means connected to said host central processing unit and said microprogram control means to apply command information received from said host central processing unit to said microprogram control means; and clock circuit means connected to said arithmetic logic operating means, said microprogram control means and said DMA interface means for generating system clocks to operate those means.
Claim 2
Dependent Claim
189 words
In a data processing system with a slave computer connecting to a host central processing unit and a host main memory, the improvement wherein said slave computer comprising: arithmetic logic operating means of which the operation cycle time is shorter than the memory cycle time of said host main memory, and computes the address of the host main memory; DMA interface means which is connected to said host main memory and said arithmetic logic operating means, directly makes an access to said host main memory by the address computed by said arithmetic logic operating means, and directly loads the result of said arithmetic logic operating means to said host main memory; microprogram control means connected to said arithmetic logic operating means and said DMA interface means for controlling those means; input/output interface means connected to said host central processing unit and said microprogram control means to apply command information received from said host central processing unit to said microprogram control means; and clock circuit means connected to said arithmetic logic operating means, said microprogram control means and said DMA interface means for generating system clocks to operate those means.
Claim 3
Dependent Claim
39 words
A data processing system according to claim 1, wherein the address computation for the host main memory and the computation of operand data taken out from said host main memory are performed together in said arithmetic logic operating means.
Claim 4
Dependent Claim
41 words
A data processing system according to claim 1, wherein said clock circuit means includes means for inhibiting the generation of system clocks in order to produce the system clock in synchronism with the memory clock cycle of said host main memory.
Claim 5
Dependent Claim
53 words
A data processing system according to claim 1, wherein said microprogram control means includes a set-up routine and a microprogram memory for storing the arithmetic logic routine, whereby executing the set-up routine, a command information supplied from said host central processing unit is fetched to branch the program to an operation routine designated.
Claim 6
Dependent Claim
101 words
A data processing system according to claim 1, wherein said DMA interface means comprises: a memory' address register for holding an address to fetch the data from said host main memory or an address to store data into said host main memory; a memory data register for holding the result of computation into said host main memory; a memory storage register for holding the data fetched from said host main memory; and a DMA controller for holding a memory request signal and a read/write signal for said host main memory, and for receiving an acknowledge signal from said host main memory.
Claim 7
Dependent Claim
81 words
A data processing system according to claim 1, wherein said microprogram control means comprises: a read only memory for storing a microprogram; a microprogram sequencer for supplying an address in which the microprogram is stored to said read only memory; a pipeline register for holding each instruction of the microprogram read out from said read only memory; a branch condition circuit for supplying control signals to said microprogram sequencer on the basis of the conditions produced from said arithmetic control means.
Claim 8
Dependent Claim
102 words
A data processing system according to claim 6, wherein said branch condition circuit comprises: a condition code selector which receives condition signals outputted from said input/output interface means and flag signals outputted from said arithmetic logic operating means, and selectively outputs those on the basis of control signals supplied from said microprogram control means; and a logic circuit connecting to the output of said condition code selector which receives a condition signal or a flag signal outputted from said condition code selector and control signal from said microprogram control means thereby to supply a branch specifying signal to said microprogram control means.
Claim 9
Dependent Claim
156 words
A data processing system according to claim 1, wherein said clock circuit means comprises: an oscillator for oscillating basic clock signals; first and second frequency-dividing flip-flop circuits which receive the basic clock signals from said oscillator and produce first and second frequency-divided clock signals; a logic multiplying circuit for receiving frequency-divided clock signals from said first and second flip-flops to produce a given timing pulse signal; a disable flip-flop which receives an output signal from said logic multiplying circuit to reset said first and second frequency-divided flip-flops thereby to halt said frequency divided clock signals; a latch circuit which receives a memory access acknowledge signal from said host main memory to produce a logical high level signal; and a synchronous flip-flop circuit which receives an output signal from said latch circuit to supply a synchronous signal to said disable flip-flop and to reset said disable flip-flop thereby to make active said first and second frequency-divided flip-flops.
References Cited (Backward Citations)
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