US5029073A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fast establishing a co-processor to memory linkage by main processor
Assignee: Hitachi Ltd
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Filing: 1986-03-06
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Granted: 1991-07-02
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Expires: 2006-03-06
Abstract
Abstract A co-processor control method intended to speed up data transfer linkage between the co-processor and memory when the co-processor is activated by the main processor, in such a way that the main processor issues an active control signal to the co-processor in the cycle of reading out an operand in the memory onto the data bus by being addressed by the main processor so that the operand on the data bus is directly delivered to the co-processor.
Inventors
- 👤 Soichi Takaya
- 👤 Yoshihiro Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:53
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F13/00; G06F13/14; G06F13/16; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
131 words
In a computer system including a main memory, a main processor for implementing basic computational functions, and co-processor for implementing special computational functions, and a data bus connected to said main memory, said main processor and said co-processor, the improvement comprising: said main processor having means for identifying an instruction to be executed by said co-processor, means for calculating an effective address of an operand of said instruction in said main memory, means for reading out said operand from said main memory onto said data bus, and means for sending to said co-processor a control signal which indicates that said main memory is outputting said operand onto said data bus; and said co-processor having means for fetching said operand from said data bus in response to receipt of said control signal.
Claim 2
Dependent Claim
131 words
In a computer system including a main memory, a main processor for implementing basic computational functions, and co-processor for implementing special computational functions, and a data bus connected to said main memory, said main processor and said co-processor, the improvement comprising: said main processor having means for identifying an instruction to be executed by said co-processor, means for calculating an effective address of an operand of said instruction in said main memory, means for reading out said operand from said main memory onto said data bus, and means for sending to said co-processor a control signal which indicates that said main memory is outputting said operand onto said data bus; and said co-processor having means for fetching said operand from said data bus in response to receipt of said control signal.
Claim 3
Dependent Claim
215 words
In a computer system including a main memory, a main processor for implementing basic computational functions, a co-processor for implementing special computational functions, and a data bus connected to said main memory, said main processor and said co-processor, the improvement comprising: said main processor having means for identifying an instruction to be executed by said co-processor, means for issuing a command to co-processor in response to identification of said instruction, means for calculating an effective address of an operand of said instruction in said main memory, means for reading out said operand from said main memory onto a data bus, and means for sending to said co-processor a control signal which indicates that said main processor is accessing said main memory in order to read out said operand onto a data bus; said co-processor having means for receiving said operand from said main memory, means for causing said receiving means to enter a wait state in response to receipt of said command issued by said main processor, and means for fetching said operand to said receiving means from said data bus in response to receipt of a data output acknowledgement signal from said main memory when said control signal has been received from said main processor while said receiving means is in said wait state.
Claim 4
Dependent Claim
215 words
In a computer system including a main memory, a main processor for implementing basic computational functions, a co-processor for implementing special computational functions, and a data bus connected to said main memory, said main processor and said co-processor, the improvement comprising: said main processor having means for identifying an instruction to be executed by said co-processor, means for issuing a command to co-processor in response to identification of said instruction, means for calculating an effective address of an operand of said instruction in said main memory, means for reading out said operand from said main memory onto a data bus, and means for sending to said co-processor a control signal which indicates that said main processor is accessing said main memory in order to read out said operand onto a data bus; said co-processor having means for receiving said operand from said main memory, means for causing said receiving means to enter a wait state in response to receipt of said command issued by said main processor, and means for fetching said operand to said receiving means from said data bus in response to receipt of a data output acknowledgement signal from said main memory when said control signal has been received from said main processor while said receiving means is in said wait state.
Claim 5
Dependent Claim
70 words
A computer system according to claim 2, wherein said receiving means comprises means which enters an operand transfer state from said wait state in response to receipt of said control signal from said main processor, and said fetching means comprises means for reading said operand from said data bus in response to a data output acknowledgement from said main memory when said receiving means is in said operand transfer state.
Claim 6
Dependent Claim
42 words
A control method according to claim 2, wherein said main processor further comprises means for indicating a state of data transfer for said operand to said co-processor, and means for transmitting said control signal to indicate said data transfer state to co-processor.
Claim 7
Dependent Claim
151 words
In a computer system including a main memory, a main processor for implementing basic computational functions, a co-processor for implementing special computational functions, and a data bus connected to said main memory, said main processor and said co-processor, the improvement comprising: said main processor having means for identifying an instruction for storing an operand held in a register of said co-processor into said main memory, means for calculating an effective address in which said operand is to be stored in said main memory, means for transmitting said address to said main memory, and means for sending to said co-processor a control signal which indicates that said main processor is accessing said main memory to initiate the storing of an operand placed on said data bus into said main memory; and said co-processor having means for outputting said operand from said register to said data bus in response to said control signal.
Claim 8
Dependent Claim
151 words
In a computer system including a main memory, a main processor for implementing basic computational functions, a co-processor for implementing special computational functions, and a data bus connected to said main memory, said main processor and said co-processor, the improvement comprising: said main processor having means for identifying an instruction for storing an operand held in a register of said co-processor into said main memory, means for calculating an effective address in which said operand is to be stored in said main memory, means for transmitting said address to said main memory, and means for sending to said co-processor a control signal which indicates that said main processor is accessing said main memory to initiate the storing of an operand placed on said data bus into said main memory; and said co-processor having means for outputting said operand from said register to said data bus in response to said control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |