Microcomputer system including a master processor and a slave processor synchronized by three control lines

Claim 1

A processing system, comprising: a master processor; a coprocessor; and a bus interconnecting said master processor and said coprocessor; said coprocessor including, first means for producing a first signal which takes an active level when said coprocessor requests that said master processor be brought into a wait condition, said first signal taking an inactive level when said coprocessor allows said master processor to perform a subsequent operation, second means for producing a second signal which takes an active level at least when said first signal is changed from an active level to an inactive level in a state of occurrence of an arithmetic exception in said coprocessor, said second signal taking an inactive level at least when said first signal is changed from an active level to an inactive level in a state of no occurrence of said arithmetic exception in said coprocessor, and third means for producing a third signal which takes an active level when said coprocessor is free of execution of an instruction and of said arithmetic exception, said third signal taking an inactive level when said coprocessor starts to execute an instruction and maintaining an inactive level until said coprocessor completes execution of said instruction, said third signal further maintaining an inactive level when said arithmetic exception occurs in said coprocessor, said master processor including, a first terminal supplied with said first signal, a second terminal supplied with said second signal, a third terminal supplied with said third signal, fourth means for transferring an instruction to be executed by said coprocessor to said coprocessor via said bus, fifth means for detecting whether or not an instruction to be executed by said coprocessor is an instruction for which said coprocessor is required to return execution resultant data to said master processor, sixth means, coupled to said third terminal and responsive to a detection result of said fifth means representing that said instruction to be executed by said coprocessor is not an instruction in which said coprocessor is required to return execution resultant data to said master processor, for detecting a level of said third signal before said coprocessor starts to execute an instruction transferred to said bus, seventh means, responsive to a detection result of said sixth means representing that said third signal is at an active level, for executing at least one instruction simultaneously with execution by said coprocessor irrespective of levels of said first and second signals, and eighth means, responsive to a detection result of said sixth means representing that said third signal is at an inactive level, for bringing said master processor into said wait condition until said first signal is changed to an inactive level and for performing a subsequent operation responsive to a level of said second signal after said first signal is changed to an inactive level.

Claim 6

A method of operating a master processor and a coprocessor, comprising the steps of: transmitting a first signal from said coprocessor to said master processor, said first signal being at an active level when said coprocessor requests that said master processor be brought into a wait condition, said first signal taking an inactive level when said coprocessor allows said master processor to perform a subsequent operation; transmitting a second signal from said coprocessor to said master processor, said second signal being at an active level at least when said first signal is changed from an active level to an inactive level while an arithmetic exception occurs in said coprocessor, said second signal taking an inactive level at least when said first signal is changed from an active level to an inactive level in a state of no occurrence of said arithmetic exception in said coprocessor; and transmitting a third signal from said coprocessor to said master processor, said third signal taking an active level when both an arithmetic exception is not occurring in said coprocessor and said coprocessor is not executing an instruction, said third signal taking an inactive level when said coprocessor starts to execute an instruction and maintaining an inactive level until said coprocessor completes execution of said instruction, said third signal further maintaining an inactive level when said arithmetic exception occurs in said coprocessor; said master processor executing at least one instruction simultaneously with execution of instructions by said coprocessor irrespective of said first and second signals, when said third signal changes to an active level; and said master processor being in a wait condition when said third signal changes to an inactive level and remaining in said wait condition until said first signal is changed to an inactive level, said master processor resuming operations after said first signal is changed to an inactive level.

Claim 7

A method of operating a master processor and a coprocessor, comprising the steps of: transmitting a first signal from said coprocessor to said master processor, said first signal being at an active level when said coprocessor requests that said master processor be brought into a wait condition, said first signal taking an inactive level when said coprocessor allows said master processor to perform a subsequent operation; transmitting a second signal from said coprocessor to said master processor, said second signal being at an active level at least when said first signal is changed from an active level to an inactive level while an arithmetic exception occurs in said coprocessor, said second signal taking an inactive level at least when said first signal is changed from an active level to an inactive level in a state of no occurrence of said arithmetic exception in said coprocessor; and transmitting a third signal from said coprocessor to said master processor, said third signal taking an active level when both an arithmetic exception is not occurring in said coprocessor and said coprocessor is not executing an instruction, said third signal taking an inactive level when said coprocessor starts to execute an instruction and maintaining an inactive level until said coprocessor completes execution of said instruction, said third signal further maintaining an inactive level when said arithmetic exception occurs in said coprocessor; said master processor executing at least one instruction simultaneously with execution of instructions by said coprocessor irrespective of said first and second signals, when said third signal changes to an active level; and said master processor being in a wait condition when said third signal changes to an inactive level and remaining in said wait condition until said first signal is changed to an inactive level, said master processor resuming operations after said first signal is changed to an inactive level.