Patent US5337088A successfully refreshed from Google Patents.
Patent US6204110B1 successfully refreshed from Google Patents.
US6204110B1
Expired / Lapsed
US
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Methods of forming an SRAM
Assignee: Micron Technology Inc
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Filing: 1999-11-04
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Granted: 2001-03-20
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Expires: 2019-11-04
Abstract
Abstract A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.
Inventors
- 👤 Martin Ceredig Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:56
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10D84/00; H10D84/201; H10D84/204; H10D84/209; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904; Y10S438/00; Y10S438/979
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
253 words
A semiconductor processing method of forming an SRAM comprising: providing a first pull down transistor having a gate, a source and a drain; providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor; providing a Vcc node; forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node; forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; and the forming of at least one of the first and second resistors comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors; forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an outer surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductor material defining the at least one of the first and second resistors.
Claim 2
Dependent Claim
253 words
A semiconductor processing method of forming an SRAM comprising: providing a first pull down transistor having a gate, a source and a drain; providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor; providing a Vcc node; forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node; forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; and the forming of at least one of the first and second resistors comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors; forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an outer surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductor material defining the at least one of the first and second resistors.
Claim 3
Dependent Claim
269 words
A semiconductor processing method of forming an SRAM, comprising: providing a first pull down transistor having a gate, a source and a drain; providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor; providing a Vcc node; forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node; forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; and the forming of at least one of the first and second resistors comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors; forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an opposing outer surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductive material comprising a first region and a second region, the first region having a different conductivity doping than the second region, the semiconductive material defining a resistor.
Claim 4
Dependent Claim
269 words
A semiconductor processing method of forming an SRAM, comprising: providing a first pull down transistor having a gate, a source and a drain; providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor; providing a Vcc node; forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node; forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; and the forming of at least one of the first and second resistors comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors; forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an opposing outer surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductive material comprising a first region and a second region, the first region having a different conductivity doping than the second region, the semiconductive material defining a resistor.
Claim 5
Dependent Claim
294 words
A semiconductor processing method of forming an SRAM comprising: providing a first pull down transistor having a gate, a source and a drain; providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor; providing a Vcc node; forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node; forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; and the forming of at least one of the first and second resistors comprising: forming a doped polysilicon layer proximate a circuit node, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors, the polysilicon comprising the one of the first and second pull down transistor gates; forming a first electrically insulative material over the doped polysilicon layer; forming a first opening in a first electrically insulative material over the circuit node, the first opening not extending to the circuit node; forming a layer of a second electrically insulative material within the first opening; forming a second opening through the layer of second electrically insulative material and through the first electrically insulative material to the circuit node; forming a resistor layer within the second opening and in electrical contact with the circuit node; and out-diffusing dopant from the doped polysilicon layer into the resistor layer.
Claim 6
Dependent Claim
294 words
A semiconductor processing method of forming an SRAM comprising: providing a first pull down transistor having a gate, a source and a drain; providing a second pull down transistor having a gate, a source and a drain; the gate of the first pull down transistor being electrically coupled to the drain of the second pull down transistor; the gate of the second pull down transistor being electrically coupled to the drain of the first pull down transistor; providing a Vcc node; forming a first resistor electrically coupled with the Vcc node; the drain of the first pull down transistor being electrically coupled through the first resistor to the Vcc node; forming a second resistor electrically coupled with the Vcc node; the drain of the second pull down transistor being electrically coupled through the second resistor to the Vcc node; and the forming of at least one of the first and second resistors comprising: forming a doped polysilicon layer proximate a circuit node, the circuit node being in electrical contact with a drain of one of the first and second pull down transistors, the polysilicon comprising the one of the first and second pull down transistor gates; forming a first electrically insulative material over the doped polysilicon layer; forming a first opening in a first electrically insulative material over the circuit node, the first opening not extending to the circuit node; forming a layer of a second electrically insulative material within the first opening; forming a second opening through the layer of second electrically insulative material and through the first electrically insulative material to the circuit node; forming a resistor layer within the second opening and in electrical contact with the circuit node; and out-diffusing dopant from the doped polysilicon layer into the resistor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-19 | 2004-09-18 | 2005-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-19 | 2008-09-18 | 2009-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-19 | 2012-09-18 | 2013-03-20 | $7700.00 | Window Closed / Lapsed |