US6039577A
Expired / Lapsed
US
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Method of forming diodes
Assignee: Micron Technology Inc
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Filing: 1998-04-09
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Granted: 2000-03-21
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Expires: 2018-04-09
Abstract
Abstract A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.
Inventors
- 👤 Martin Ceredig Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:21
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10D84/00; H10D84/201; H10D84/204; H10D84/209; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904; Y10S438/00; Y10S438/979
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
231 words
A semiconductor processing method of forming a back-to-back diode construction, comprising: providing a circuit node; forming a first electrically insulative material outwardly of the node; forming an opening in the first electrically insulative material over the node, the opening having an opening width and sidewalls; forming a second electrically insulative material outwardly of the first material and within the opening to a thickness which is less than one-half the opening width to less than completely fill the opening with second electrically insulative material, the first and second materials being selectively etchable relative to one another; anisotropically etching the second material to form a substantially vertically extending sidewall spacer within the opening and to outwardly expose an upper surface of the first material adjacent the sidewall spacer, the sidewall spacer having an inner lateral surface and an outer lateral surface; removing a portion of the first material to outwardly expose at least a portion of the sidewall spacer outer lateral surface; providing a conformal layer of a semiconductive material over the exposed outer lateral sidewall spacer surface and over the inner lateral sidewall spacer surface within the opening to define a container shape of semiconductive material within the opening, the container shape making electrical connection with the circuit node; and doping the conformal layer to define two discrete doped regions separated by an intervening region, the doped conformal layer comprising back-to-back diodes.
Claim 2
Dependent Claim
231 words
A semiconductor processing method of forming a back-to-back diode construction, comprising: providing a circuit node; forming a first electrically insulative material outwardly of the node; forming an opening in the first electrically insulative material over the node, the opening having an opening width and sidewalls; forming a second electrically insulative material outwardly of the first material and within the opening to a thickness which is less than one-half the opening width to less than completely fill the opening with second electrically insulative material, the first and second materials being selectively etchable relative to one another; anisotropically etching the second material to form a substantially vertically extending sidewall spacer within the opening and to outwardly expose an upper surface of the first material adjacent the sidewall spacer, the sidewall spacer having an inner lateral surface and an outer lateral surface; removing a portion of the first material to outwardly expose at least a portion of the sidewall spacer outer lateral surface; providing a conformal layer of a semiconductive material over the exposed outer lateral sidewall spacer surface and over the inner lateral sidewall spacer surface within the opening to define a container shape of semiconductive material within the opening, the container shape making electrical connection with the circuit node; and doping the conformal layer to define two discrete doped regions separated by an intervening region, the doped conformal layer comprising back-to-back diodes.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein the intervening region is doped with a conductivity-enhancing dopant.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein the two discrete doped regions comprise a conductivity-enhancing dopant of a different type than a conductivity-enhancing dopant in the intervening region.
Claim 5
Dependent Claim
36 words
The method of claim 1 wherein the two discrete doped regions comprise an n-type conductivity-enhancing dopant provided to a concentration of at least 1×10 19 atoms/cm 3 and the intervening region comprises a p-type conductivity-enhancing dopant.
Claim 6
Dependent Claim
39 words
The method of claim 1 wherein the step of forming the opening in the first electrically insulative material over the circuit node does not outwardly expose the circuit node prior to the formation of the second electrically insulative material.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein the first material comprises silicon dioxide and the second material comprises silicon nitride.
Claim 8
Dependent Claim
116 words
A semiconductor processing method of forming a back-to-back diode comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made; forming a substantially vertically extending sidewall spacer within the opening, the sidewall spacer having an inner lateral surface and an outer lateral surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer lateral surface and over the sidewall spacer inner lateral surface, the semiconductor material being doped to form two discrete doped regions separated by an intervening region, the layer of doped semiconductive material defining a back-to-back diode in electrical connection with the circuit node.
Claim 9
Dependent Claim
116 words
A semiconductor processing method of forming a back-to-back diode comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made; forming a substantially vertically extending sidewall spacer within the opening, the sidewall spacer having an inner lateral surface and an outer lateral surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer lateral surface and over the sidewall spacer inner lateral surface, the semiconductor material being doped to form two discrete doped regions separated by an intervening region, the layer of doped semiconductive material defining a back-to-back diode in electrical connection with the circuit node.
Claim 10
Dependent Claim
15 words
The method of claim 7 wherein the intervening region is doped with a conductivity-enhancing dopant.
Claim 11
Dependent Claim
27 words
The method of claim 7 wherein the two discrete doped regions comprise a conductivity-enhancing dopant of a different type than a conductivity-enhancing dopant in the intervening region.
Claim 12
Dependent Claim
36 words
The method of claim 7 wherein the two discrete doped regions comprise an n-type conductivity-enhancing dopant provided to a concentration of at least 1×10 19 atoms/cm 3 and the intervening region comprises a p-type conductivity-enhancing dopant.
Claim 13
Dependent Claim
16 words
The method of claim 7 wherein the circuit node comprises an implant in a semiconductor substrate.
Claim 14
Dependent Claim
125 words
A semiconductor processing method of forming a back-to-back diode, comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made; forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an opposing outer surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductive material comprising a first region, a second region and a third region, the second region separating the first and third regions and having a different conductivity doping than the first and third regions, the semiconductive material defining a back-to-back diode in electrical connection with the node.
Claim 15
Dependent Claim
125 words
A semiconductor processing method of forming a back-to-back diode, comprising: forming an opening in a first electrically insulative material over a circuit node to which electrical connection is to be made; forming a sidewall spacer within the opening, the sidewall spacer having an inner surface and an opposing outer surface and comprising a second insulative material; and forming a layer of a semiconductive material over the sidewall spacer outer surface and over the sidewall spacer inner surface, the semiconductive material comprising a first region, a second region and a third region, the second region separating the first and third regions and having a different conductivity doping than the first and third regions, the semiconductive material defining a back-to-back diode in electrical connection with the node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-21 | 2003-09-20 | 2004-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-21 | 2007-09-20 | 2008-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-21 | 2011-09-20 | 2012-03-21 | $7700.00 | Window Closed / Lapsed |