US5241206A
Expired / Lapsed
US
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Self-aligned vertical intrinsic resistance
Assignee: Micron Technology Inc
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Filing: 1992-10-02
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Granted: 1993-08-31
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Expires: 2012-10-02
Abstract
Abstract A self-aligned vertical intrinsic resistance for use in semiconductor devices is developed. The self-aligned vertical intrinsic resistance may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The vertical positioning of the intrinsic resistance not only takes up less die space but also allows for a simple process to construct the resistance by eliminating a photomask step that is normally required prior to implanting an intrinsic resistance used in conventional fabrication processes.
Inventors
- 👤 Ruojia Lee
- 👤 Monte Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:20
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
71 words
An intrinsic resistance for a semiconductor device fabricated on a wafer substrate, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductor portion forming said intrinsic resistance, said intrinsic resistance comprising a light doping of first type conductivity; and c) said horizontal semiconductive portions conductively doped as a second type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 2
Dependent Claim
71 words
An intrinsic resistance for a semiconductor device fabricated on a wafer substrate, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductor portion forming said intrinsic resistance, said intrinsic resistance comprising a light doping of first type conductivity; and c) said horizontal semiconductive portions conductively doped as a second type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 3
Dependent Claim
13 words
The intrinsic resistance of claim 1, wherein said first type conductivity is p-type.
Claim 4
Dependent Claim
13 words
The intrinsic resistance of claim 1, wherein said first type conductivity is n-type.
Claim 5
Dependent Claim
13 words
The intrinsic resistance of claim 1, wherein said second type conductivity is n-type.
Claim 6
Dependent Claim
13 words
The intrinsic resistance of claim 1, wherein said second type conductivity is p-type.
Claim 7
Dependent Claim
74 words
A substantially vertical intrinsic resistance for a semiconductor device fabricated on a wafer substrate, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductive portion forming said vertical intrinsic resistance, said intrinsic resistance comprising a light doping of first type conductivity; and c) said horizontal semiconductive portions conductively doped as a second type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 8
Dependent Claim
74 words
A substantially vertical intrinsic resistance for a semiconductor device fabricated on a wafer substrate, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductive portion forming said vertical intrinsic resistance, said intrinsic resistance comprising a light doping of first type conductivity; and c) said horizontal semiconductive portions conductively doped as a second type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 9
Dependent Claim
13 words
The intrinsic resistance of claim 6, wherein said first type conductivity is p-type.
Claim 10
Dependent Claim
13 words
The intrinsic resistance of claim 6, wherein said second type conductivity is n-type.
Claim 11
Dependent Claim
13 words
The intrinsic resistance of claim 6, wherein said first type conductivity is n-type.
Claim 12
Dependent Claim
13 words
The intrinsic resistance of claim 6, wherein said second type conductivity is p-type.
Claim 13
Dependent Claim
13 words
The intrinsic resistance of claim 6, wherein said resistance forms a pullup resistor.
Claim 14
Dependent Claim
13 words
The intrinsic resistance of claim 6, wherein said resistance forms a pulldown resistor.
Claim 15
Dependent Claim
16 words
The intrinsic resistance of claim 6, wherein said semiconductor device is a static random access memory.
Claim 16
Dependent Claim
73 words
A static random access memory fabricated on a substrate having an intrinsic resistance, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductive vertical portion forming said intrinsic resistance, said intrinsic resistance comprising a light doping of first type conductivity; and c) said horizontal semiconductive portions conductively doped as a second type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 17
Dependent Claim
73 words
A static random access memory fabricated on a substrate having an intrinsic resistance, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductive vertical portion forming said intrinsic resistance, said intrinsic resistance comprising a light doping of first type conductivity; and c) said horizontal semiconductive portions conductively doped as a second type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 18
Dependent Claim
13 words
The intrinsic resistance of claim 14, wherein said first type conductivity is p-type.
Claim 19
Dependent Claim
13 words
The intrinsic resistance of claim 14, wherein said first type conductivity is n-type.
Claim 20
Dependent Claim
13 words
The intrinsic resistance of claim 14, wherein said second type conductivity is n-type.
Claim 21
Dependent Claim
13 words
The intrinsic resistance of claim 14, wherein said second type conductivity is p-type.
Claim 22
Dependent Claim
75 words
A static random access memory fabricated on a wafer substrate having a substantially vertical intrinsic resistance, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductive portion forming said vertical intrinsic resistance, said intrinsic resistance comprising a light doping of p-type conductivity; and c) said horizontal semiconductive horizontal portions conductively doped as an n-type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 23
Dependent Claim
75 words
A static random access memory fabricated on a wafer substrate having a substantially vertical intrinsic resistance, said resistance comprising: a) a layer of semiconductive material having substantially horizontal and substantially vertical semiconductive portions; b) said vertical semiconductive portion forming said vertical intrinsic resistance, said intrinsic resistance comprising a light doping of p-type conductivity; and c) said horizontal semiconductive horizontal portions conductively doped as an n-type conductivity, said horizontal semiconductive portions providing low resistive coupling sections.
Claim 24
Dependent Claim
13 words
The intrinsic resistance of claim 19, wherein said resistance forms a pullup resistor.
Claim 25
Dependent Claim
13 words
The intrinsic resistance of claim 19, wherein said resistance forms a pulldown resistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-30 | 1997-03-01 | 1997-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-30 | 2001-03-01 | 2001-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-30 | 2005-03-01 | 2005-08-31 | $7700.00 | Window Closed / Lapsed |