US4690728A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pattern delineation of vertical load resistor
Assignee: Intel Corp
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Filing: 1986-10-23
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Granted: 1987-09-01
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Expires: 2006-10-23
Abstract
Abstract A process for delineating a vertical resistor on a semiconductor device is disclosed. Resistive and diffusion barrier layers are deposited and then etched, first by dry plasma and then by wet bath. The two step etching allows complete removal of the deposited layers with minimal damage to exposed dielectric, silicide, polysilicon or doped regions on the semiconductor.
Inventors
- 👤 Chi-Hwa Tsang
- 👤 Galen Kawamoto
- 👤 Leopoldo D. Yau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:33
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10B; H10B10/00; H10B10/15; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49099
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
55 words
A process for patterning a resistive layer of a semiconductor device, comprising the steps of: depositing an electrically resistive layer; etching in dry plasma to remove an unmasked portion of said resistive layer; etching in a wet bath to remove remnants of said unmasked portion; whereby a vertical resistor is formed on said semiconductor device.
Claim 2
Dependent Claim
55 words
A process for patterning a resistive layer of a semiconductor device, comprising the steps of: depositing an electrically resistive layer; etching in dry plasma to remove an unmasked portion of said resistive layer; etching in a wet bath to remove remnants of said unmasked portion; whereby a vertical resistor is formed on said semiconductor device.
Claim 3
Dependent Claim
17 words
The process of claim 1, wherein said dry plasma is comprised of C 2 F 6 .
Claim 4
Dependent Claim
17 words
The process of claim 2, wherein said wet bath is comprised of H 3 PO 4 .
Claim 5
Dependent Claim
15 words
The process of claim 3, wherein said resistive layer is comprised of silicon-rich silicon nitride.
Claim 6
Dependent Claim
15 words
The process of claim 4, wherein said semiconductor device is formed on a silicon substrate.
Claim 7
Dependent Claim
18 words
The process of claim 5, further including the step of forming a barrier layer above said vertical resistor.
Claim 8
Dependent Claim
116 words
A process for patterning a resistor on a semiconductor device, comprising the steps of: depositing an electrically resistive layer; depositing a barrier layer on said resistive le, comprising the steps of: depositing an electrically resistive layer; depositing a barrier layer on said resistive layer; masking a portion of said resistive and barrier layers where said resistor is to be formed; etching in a first dry plasma etch cycle to remove an unmasked portion of said barrier layer; etching in a second dry plasma etch cycle to remove an unmasked portion of said resistive layer; etching in a wet bath to remove remnants of said unmasked portions; whereby a vertical resistor is formed on said semiconductor device.
Claim 9
Dependent Claim
116 words
A process for patterning a resistor on a semiconductor device, comprising the steps of: depositing an electrically resistive layer; depositing a barrier layer on said resistive le, comprising the steps of: depositing an electrically resistive layer; depositing a barrier layer on said resistive layer; masking a portion of said resistive and barrier layers where said resistor is to be formed; etching in a first dry plasma etch cycle to remove an unmasked portion of said barrier layer; etching in a second dry plasma etch cycle to remove an unmasked portion of said resistive layer; etching in a wet bath to remove remnants of said unmasked portions; whereby a vertical resistor is formed on said semiconductor device.
Claim 10
Dependent Claim
21 words
The process of claim 7, wherein said first dry plasma etch cycle is comprised of a first plasma formed from chlorine.
Claim 11
Dependent Claim
25 words
The process of claim 8, wherein said second dry plasma etch cycle is comprised of a second plasma formed from C 2 F 6 .
Claim 12
Dependent Claim
19 words
The process of claim 9, wherein said wet bath is performed in H 3 PO 4 and deionized water.
Claim 13
Dependent Claim
15 words
The process of claim 10, wherein said resistive layer is comprised of silicon-rich silicon nitride.
Claim 14
Dependent Claim
14 words
The process of claim 11, wherein said barrier layer is comprised of titanium nitride.
Claim 15
Dependent Claim
15 words
The process of claim 12, wherein said semiconductor device is formed on a silicon substrate.
Claim 16
Dependent Claim
12 words
The process of claim 13, wherein said second plasmas further including oxygen.
Claim 17
Dependent Claim
14 words
The process of claim 14, wherein said first and second plasma further including helium.
Claim 18
Dependent Claim
118 words
A process for patterning a resistor on a semiconductor device, comprising the steps of: depositing an electrically resisive layer on an underlying layer; depositing a barrier layer on said resistive layer; masking a portion of said resistive and barrier layers where said resistor is to be formed; etching in a first dry plasma etch cycle to remove an unmasked portion of said barrier layer; etching in a second dry plasma etch cycle to remove an unmasked portion of said resistive layer, but terminating said second dry plasma etch as soon as said underlying layer is exposed; etching in a wet bath to remove remnants of said unmasked portions; whereby a vertical resistor is formed on said semiconductor device.
Claim 19
Dependent Claim
118 words
A process for patterning a resistor on a semiconductor device, comprising the steps of: depositing an electrically resisive layer on an underlying layer; depositing a barrier layer on said resistive layer; masking a portion of said resistive and barrier layers where said resistor is to be formed; etching in a first dry plasma etch cycle to remove an unmasked portion of said barrier layer; etching in a second dry plasma etch cycle to remove an unmasked portion of said resistive layer, but terminating said second dry plasma etch as soon as said underlying layer is exposed; etching in a wet bath to remove remnants of said unmasked portions; whereby a vertical resistor is formed on said semiconductor device.
Claim 20
Dependent Claim
42 words
The process of claim 16, wherein said first dry plasma etch cycle is comprised of a first plasma formed from Cl 2 , circulated at 50-200 sccm at a pressure of 300-500 millitorr and having a radio frequency power at 250-350 watts.
Claim 21
Dependent Claim
18 words
The process of claim 17, wherein said first dry plasma etch cycle includes introducing helium at 0-100 sccm.
Claim 22
Dependent Claim
44 words
The process of claim 18, wherein said second dry plasma etch cycle is comprised of a second plasma formed from C 2 F 6 , circulated at 50-200 sccm at a pressure of 300-700 millitorr and having a radio frequency power of 200-400 watts.
Claim 23
Dependent Claim
19 words
The process of claim 19, wherein said wet bath is performed in H 3 PO 4 and deionized water.
Claim 24
Dependent Claim
23 words
The process of claim 20, further including a step of forming a photoresistive layer on said barrier layer after depositing said barrier layer.
Claim 25
Dependent Claim
15 words
The process of claim 21, wherein said resistive layer is comprised of silicon-rich silicon nitride.
Claim 26
Dependent Claim
14 words
The process of claim 22, wherein said barrier layer is comprised of titanium nitride.
Claim 27
Dependent Claim
15 words
The process of claim 23, wherein said semiconductor device is formed on a silicon substrate.
Claim 28
Dependent Claim
13 words
The process of claim 24, wherein said underlying layer is a dielectric layer.
Claim 29
Dependent Claim
11 words
The process of claim 25, wherein said dielectric layer is glass.
Claim 30
Dependent Claim
21 words
The process of claim 26, wherein said first plasma further including helium and said second plasma further including oxygen and helium.
Claim 31
Dependent Claim
13 words
The process of claim 24, wherein said underlying layer is comprised of polysilicon.
Claim 32
Dependent Claim
13 words
The prociss of claim 24, wherein said underlying layer is comprised of polycide.
Claim 33
Dependent Claim
15 words
The process of claim 24, wherein said underlying layer is comprised of a silicon substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-31 | 1991-03-02 | 1991-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-31 | 1995-03-02 | 1995-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-31 | 1999-03-02 | 1999-09-01 | $7700.00 | Window Closed / Lapsed |