Semiconductor integrated circuit memory device

Claim 2

A semiconductor integrated circuit memory device comprising a pluraltiy of static type memory cells, each memory cell including first, second, third and fourth insulated gate field effect transistors formed in a semiconductor substrate and first and second load elements, one of source and drain regions of said first transistor being coupled to one of source and drain regions of said third transistor, to the gate electrode of said second transistor and to one end of said first load element, one of source and drain regions of said second transistor being coupled to one of source and drain regions of said fourth transistor, to the gate electrode of said first transistor and to one end of said second load element, a first data line extending in a first direction and connected to the other of source and drain regions of said third transistor, a second data line extending in said first direction and connected to the other of source and drain regions of said fourth transistor, a first power supply line extending in a second direction perpendicular to said first direction and connected to the other ends of said first and second load elements, respectively, a word line extending in said second direction and coupled to gate electrodes of said third and fourth transistors, and a second power supply line extending in said second direction and connected to the other of source and drain regions of said first transistor and to the other of source and drain regions of said second transistor, respectively, said second power supply line being formed of a first metallic layer, and said first and second data lines being formed of a second metallic layer and crossing said second power supply line with an insulating layer interposed therebetween.

Claim 3

A semiconductor integrated circuit memory device as claimed in claim 1, in which said word line and gate electrodes of said first, second, third and fourth transistors are formed of a first polycrystalline silicon layer at a first level, said first power supply line being formed of a second polycrystalline silicon layer at a second level, said second power supply line being positioned at a third level, and said first and second data lines being positioned at a fourth level.

Claim 4

A semiconductor integrated circuit memory device as claimed in claim 2, in which said load elements are formed of said second polycrystalline silicon layer.

Claim 5

A semiconductor integrated circuit memory device as claimed in claim 2, in which said word line includes a first word wiring layer made of said first polycrystalline silicon layer, extending in said second direction and forming said gate electrodes of said third and fourth transistors, and a second word wiring layer made of a metallic layer of the same level as that of said first metallic layer, every three or more of said memory cells being grouped into a memory cell block, and said first and second word wiring layers are connected with each other at one location for every one of said memory cell blocks.

Claim 6

A semiconductor integrated circuit memory device as claimed in claim 1, in which said word line includes a first word wiring layer made of polycrystalline silicon, extending in said second direction and forming said gate electrodes of said third and fourth transistors, and a second word wiring layer made of a metallic layer at the same level as that of said first metallic layer and extending substantially in parallel to said first word wiring layer, every three or more of said memory cells being grouped into a memory cell block, and said first and second word wiring layers being connected with each other at one location for every one of said memory cell blocks.

Claim 7

A semiconductor integrated circuit memory device as claimed in claim 1, in which said first and second metallic layers are made of aluminium or aluminium alloy.

Claim 8

A semiconductor integrated circuit memory device comprising a plurality of memory cells arranged in one direction in a semiconductor substrate, each memory cell including a plurality of insulated gate type field effect transistors, and a word line including a first word wiring layer made of polycrystalline silicon extending in said one direction and forming each gate electrode of two of said transistors and a second word wiring layer made of metallic material extending substantially in parallel to said first word wiring layer, said first and second word wiring layers being connected with each other at one location for every three or more memory cells.

Claim 9

A semiconductor integrated circuit memory device comprising a plurality of memory cells arranged in one direction in a semiconductor substrate, each memory cell including a plurality of insulated gate type field effect transistors, and a word line including a first word wiring layer made of polycrystalline silicon extending in said one direction and forming each gate electrode of two of said transistors and a second word wiring layer made of metallic material extending substantially in parallel to said first word wiring layer, said first and second word wiring layers being connected with each other at one location for every three or more memory cells.

Claim 10

A semiconductor integrated circuit memory device comprising a plurality of static type memory cells, each memory cell including first, second, third and fourth insulated gate field effect transistors formed in a semiconductor substrate and first and second load elements, one of source and drain regions of said first transistor being coupled to one of source and drain regions of said third transistor, to the gate electrode of said second transistor and to one end of said first load elements, one of source and drain regions of said second transistor being coupled to one of source and drain regions of said fourth transistor, to the gate electrode of said first transistor and to one end of said second load element, a first power supply line extending in a first direction and connected to other ends of said first and second load elements, respectively, a word line extending in said first direction and coupled to gate electrodes of said third and fourth transistors, respectively, a second power supply line extending in said first direction and connected to the other of source and drain regions of said first and second transistors, respectively, through openings formed in a first insulating layer, said second power supply line being made of a first metallic layer of a first level, first and a second intermediate electrode layers made of said first metallic layer of said first level connected to the others of source and drain regions of said third and fourth transistors, respectively, through openings formed in said first insulating layer, respectively, a second insulating layer covering said power supply line and said intermediate electrode layers and having first and second apparatus exposing respective portions of said first and second intermediate electrode layers, a first data line connected to said first intermediate electrode layer through said first aperture and extending on the surface of said second insulating layer in a second direction perpendicular to said first direction, said first data line being made of a second metallic layer of a second level above said first level, and a second data line extending on said second insulating layer in said second direction, made of said second metallic layer and electrically connected to said second intermediate electrode layer via said second aperture.

Claim 11

A semiconductor integrated circuit memory device comprising a plurality of static type memory cells, each memory cell including first, second, third and fourth insulated gate field effect transistors formed in a semiconductor substrate and first and second load elements, one of source and drain regions of said first transistor being coupled to one of source and drain regions of said third transistor, to the gate electrode of said second transistor and to one end of said first load elements, one of source and drain regions of said second transistor being coupled to one of source and drain regions of said fourth transistor, to the gate electrode of said first transistor and to one end of said second load element, a first power supply line extending in a first direction and connected to other ends of said first and second load elements, respectively, a word line extending in said first direction and coupled to gate electrodes of said third and fourth transistors, respectively, a second power supply line extending in said first direction and connected to the other of source and drain regions of said first and second transistors, respectively, through openings formed in a first insulating layer, said second power supply line being made of a first metallic layer of a first level, first and a second intermediate electrode layers made of said first metallic layer of said first level connected to the others of source and drain regions of said third and fourth transistors, respectively, through openings formed in said first insulating layer, respectively, a second insulating layer covering said power supply line and said intermediate electrode layers and having first and second apparatus exposing respective portions of said first and second intermediate electrode layers, a first data line connected to said first intermediate electrode layer through said first aperture and extending on the surface of said second insulating layer in a second direction perpendicular to said first direction, said first data line being made of a second metallic layer of a second level above said first level, and a second data line extending on said second insulating layer in said second direction, made of said second metallic layer and electrically connected to said second intermediate electrode layer via said second aperture.

Claim 12

A semiconductor integrated circuit memory device as claimed in claim 8, in which said first and second metallic layers are made of aluminum or aluminum alloy.