US6194262B1
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US
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Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors
Assignee: Round Rock Research LLC
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Filing: 2000-03-29
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Granted: 2001-02-27
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Expires: 2020-03-29
Abstract
Abstract An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.
Inventors
- 👤 Wendell P. Noble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:43
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/48; H10B12/488; H10B12/31; H10B12/312; H10B12/485; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; Y; Y10; Y10S; Y10S257/00; Y10S257/905; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
75 words
An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising: a semiconductor device formed in a semiconductor substrate; a first conductor formed outwardly from the first semiconductor device, the first conductor having a width less than the minimum lithographic dimension; a second conductor formed outwardly from the first semiconductor device, the second conductor adjacent to the first conductor; and a circuit element coupled to the semiconductor device by the second conductor.
Claim 2
Dependent Claim
75 words
An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising: a semiconductor device formed in a semiconductor substrate; a first conductor formed outwardly from the first semiconductor device, the first conductor having a width less than the minimum lithographic dimension; a second conductor formed outwardly from the first semiconductor device, the second conductor adjacent to the first conductor; and a circuit element coupled to the semiconductor device by the second conductor.
Claim 3
Dependent Claim
58 words
The integrated circuit according to claim 1 further comprising a bit line formed outwardly from the semiconductor device and wherein the circuit element is a storage capacitor, the semiconductor device is a transistor for coupling the bit line to the storage capacitor through the second conductor, and the first conductor is a word line for activating the transistor.
Claim 4
Dependent Claim
21 words
The integrated circuit according to claim 2 wherein the second conductor and the bit line are bounded by the word line.
Claim 5
Dependent Claim
23 words
The integrated circuit device according to claim 2 wherein the bit line and the storage capacitor are formed using a single mask image.
Claim 6
Dependent Claim
160 words
A memory device formed by a lithographic process having a minimum lithographic dimension, comprising: a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor; a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines; and a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor.
Claim 7
Dependent Claim
160 words
A memory device formed by a lithographic process having a minimum lithographic dimension, comprising: a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor; a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines; and a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor.
Claim 8
Dependent Claim
20 words
The memory device according to claim 5 wherein the conductors and the bit line are bounded by the word lines.
Claim 9
Dependent Claim
22 words
The memory device according to claim 5 wherein the bit line and the storage capacitors are formed using a single mask image.
Claim 10
Dependent Claim
163 words
A pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension, comprising: two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors; a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistors, the bit line and the two conductors adjacent to the word line; and two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors.
Claim 11
Dependent Claim
163 words
A pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension, comprising: two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors; a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistors, the bit line and the two conductors adjacent to the word line; and two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors.
Claim 12
Dependent Claim
22 words
The pair of memory cells according to claim 8 wherein the conductors and the bit line are bounded by the word lines.
Claim 13
Dependent Claim
25 words
The pair of memory cells according to claim 8 wherein the bit line and the storage capacitors are formed by using a single mask image.
Claim 14
Dependent Claim
123 words
A semiconductor memory device formed using a lithographic process having a minimum lithographic dimension, comprising: a transistor formed in a semiconductor substrate; a word line formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension, wherein the word line is used to activate the transistor; a bit line formed outwardly from the transistor which is coupled to the transistor, wherein the bit line is adjacent to the word line; a conductor formed outwardly from the transistor which is coupled to the transistor, wherein the conductor is adjacent to the word line; and a storage capacitor formed outwardly from the bit line and the conductor, wherein the storage capacitor is coupled to the transistor by the conductor.
Claim 15
Dependent Claim
123 words
A semiconductor memory device formed using a lithographic process having a minimum lithographic dimension, comprising: a transistor formed in a semiconductor substrate; a word line formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension, wherein the word line is used to activate the transistor; a bit line formed outwardly from the transistor which is coupled to the transistor, wherein the bit line is adjacent to the word line; a conductor formed outwardly from the transistor which is coupled to the transistor, wherein the conductor is adjacent to the word line; and a storage capacitor formed outwardly from the bit line and the conductor, wherein the storage capacitor is coupled to the transistor by the conductor.
Claim 16
Dependent Claim
21 words
The semiconductor memory device of claim 11 , wherein the conductor and the bit line are bounded by the word line.
Claim 17
Dependent Claim
24 words
The semiconductor memory device of claim 11 , wherein the bit line is self aligned with the storage capacitor using a single mask image.
Claim 18
Independent Claim
98 words
A method for forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising the steps of: forming a semiconductor device in a semiconductor substrated; forming a first conductor outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension; forming a second conductor outwardly from the semiconductor device, the second conductor adjacent to and bounded by the first conductor; and coupling a storage capacitor to the semiconductor device by the second conductor, wherein the second conductor is self-aligned with the storage capacitor by using a single mask image.
Claim 19
Independent Claim
98 words
A method for forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising the steps of: forming a semiconductor device in a semiconductor substrated; forming a first conductor outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension; forming a second conductor outwardly from the semiconductor device, the second conductor adjacent to and bounded by the first conductor; and coupling a storage capacitor to the semiconductor device by the second conductor, wherein the second conductor is self-aligned with the storage capacitor by using a single mask image.
Claim 20
Dependent Claim
20 words
The method of claim 14 , wherein forming a semiconductor device comprises forming a transistor for accessing the storage capacitor.
Claim 21
Dependent Claim
20 words
The method of claim 15 , wherein forming a first conductor comprises forming a word line for activating the transistor.
Claim 22
Independent Claim
224 words
A method of fabricating two memory cells having a shared bit line using a lithographic process having a minimum lithographic dimension, comprising: forming two transistors in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate extending outwardly from the semiconductor substrate; forming two word lines outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, one word line connected to a gate of one of the two transistors and one word line connected to the other for activating the transistor; forming a bit line and two conductors outwardly from the transistors that couple to the transistor, the bit line coupled to the shared drain of the transistors, one conductor coupled to a source of one of the two transistors and one conductor coupled to a source of the other transistor, the bit line and the conductors adjacent to and bounded by the word lines; and forming two storage capacitors outwardly from the bit line and the conductors, one storage capacitor coupled to a source of one of the two transistors by one of the conductors and one storage capacitor coupled to a source of the other transistor by the other conductor, wherein the bit line is self-aligned with the one storage capacitor by using a single mask image.
Claim 23
Independent Claim
224 words
A method of fabricating two memory cells having a shared bit line using a lithographic process having a minimum lithographic dimension, comprising: forming two transistors in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate extending outwardly from the semiconductor substrate; forming two word lines outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, one word line connected to a gate of one of the two transistors and one word line connected to the other for activating the transistor; forming a bit line and two conductors outwardly from the transistors that couple to the transistor, the bit line coupled to the shared drain of the transistors, one conductor coupled to a source of one of the two transistors and one conductor coupled to a source of the other transistor, the bit line and the conductors adjacent to and bounded by the word lines; and forming two storage capacitors outwardly from the bit line and the conductors, one storage capacitor coupled to a source of one of the two transistors by one of the conductors and one storage capacitor coupled to a source of the other transistor by the other conductor, wherein the bit line is self-aligned with the one storage capacitor by using a single mask image.
Claim 24
Dependent Claim
126 words
An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising: a transistor formed in a semiconductor substrate; a bit line formed outwardly from the transistor; a word line for activating the transistor formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension; a first conductor formed outwardly from the transistor, the second conductor adjacent to the word line, wherein the first conductor and the bit line are bounded by the word line; and a storage capacitor coupled to the transistor by the word line, wherein the transistor couples the bit line to the storage capacitor through the first conductor and wherein the bit line and the storage capacitor are formed using a single mask image.
Claim 25
Dependent Claim
126 words
An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising: a transistor formed in a semiconductor substrate; a bit line formed outwardly from the transistor; a word line for activating the transistor formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension; a first conductor formed outwardly from the transistor, the second conductor adjacent to the word line, wherein the first conductor and the bit line are bounded by the word line; and a storage capacitor coupled to the transistor by the word line, wherein the transistor couples the bit line to the storage capacitor through the first conductor and wherein the bit line and the storage capacitor are formed using a single mask image.
Claim 26
Dependent Claim
188 words
A memory device formed by a lithographic process having a minimum lithographic dimension, comprising: a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor; a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines; a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor; and wherein the conductors and the bit line are bounded by the word lines and the bit line and the storage capacitors are formed using a single mask image.
Claim 27
Dependent Claim
188 words
A memory device formed by a lithographic process having a minimum lithographic dimension, comprising: a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor; a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines; a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor; and wherein the conductors and the bit line are bounded by the word lines and the bit line and the storage capacitors are formed using a single mask image.
Claim 28
Dependent Claim
193 words
A pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension, comprising: two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors; a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistors, the bit line and the two conductors adjacent to the word line and wherein the conductors and the bit line are bounded by the word lines; and two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors, wherein the bit line and the storage capacitors are formed by using a single mask image.
Claim 29
Dependent Claim
193 words
A pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension, comprising: two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate; two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors; a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistors, the bit line and the two conductors adjacent to the word line and wherein the conductors and the bit line are bounded by the word lines; and two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors, wherein the bit line and the storage capacitors are formed by using a single mask image.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-27 | 2004-08-28 | 2005-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-27 | 2008-08-28 | 2009-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-27 | 2012-08-28 | 2013-02-27 | $7700.00 | Window Closed / Lapsed |