US5753527A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1996-03-11
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Granted: 1998-05-19
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Expires: 2016-03-11
Abstract
Abstract A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.
Inventors
- 👤 Hiromi Itoh
- 👤 Tomonori Okudaira
- 👤 Keiichiro Kashihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:57
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/01; H10B12/09; H10B12/02; H10B12/03
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
261 words
A method of manufacturing a semiconductor memory device including a memory cell portion and a peripheral circuit portion on a main surface of a semiconductor substrate, said memory cell portion including memory cells for storing information and said peripheral circuit portion including peripheral circuits for controlling an operation of said memory cells, comprising the steps of: forming a first interlayer insulating film to cover said memory cell portion and said peripheral circuit portion; forming in said first interlayer insulating film a first opening to expose a part of said memory cell portion, and a second opening to expose a part of said peripheral circuit portion; forming first and second plug electrodes, electrically connected to the part of said memory cell portion and the part of said peripheral circuit portion, in said first and second openings, respectively; forming a conductive layer to cover top surfaces of said first and second plug electrodes and a top surface of said first interlayer insulating film; patterning said conductive layer to form a capacitor lower electrode on said top surface of said first plug electrode and form a pad layer on said top surface of said second plug electrode; sequentially forming a capacitor dielectric film and a capacitor upper electrode to cover said capacitor lower electrode; forming a second interlayer insulating film to cover said pad layer and said capacitor upper electrode; forming a third opening at said second interlayer insulating film located above said pad electrode; and forming an interconnection layer, which is electrically connected to said pad layer, at least in said third opening.
Claim 2
Independent Claim
261 words
A method of manufacturing a semiconductor memory device including a memory cell portion and a peripheral circuit portion on a main surface of a semiconductor substrate, said memory cell portion including memory cells for storing information and said peripheral circuit portion including peripheral circuits for controlling an operation of said memory cells, comprising the steps of: forming a first interlayer insulating film to cover said memory cell portion and said peripheral circuit portion; forming in said first interlayer insulating film a first opening to expose a part of said memory cell portion, and a second opening to expose a part of said peripheral circuit portion; forming first and second plug electrodes, electrically connected to the part of said memory cell portion and the part of said peripheral circuit portion, in said first and second openings, respectively; forming a conductive layer to cover top surfaces of said first and second plug electrodes and a top surface of said first interlayer insulating film; patterning said conductive layer to form a capacitor lower electrode on said top surface of said first plug electrode and form a pad layer on said top surface of said second plug electrode; sequentially forming a capacitor dielectric film and a capacitor upper electrode to cover said capacitor lower electrode; forming a second interlayer insulating film to cover said pad layer and said capacitor upper electrode; forming a third opening at said second interlayer insulating film located above said pad electrode; and forming an interconnection layer, which is electrically connected to said pad layer, at least in said third opening.
Claim 3
Dependent Claim
53 words
The method of manufacturing a semiconductor memory device according to claim 1, wherein said step of forming said pad layer includes the step of forming said pad layer such that said pad layer extends over said top surface of said second plug electrode and said top surface of said first interlayer insulating film.
Claim 4
Dependent Claim
40 words
The method of manufacturing a semiconductor memory device according to claim 1, wherein said conductive layer is made of noble metal having a high melting point, and said capacitor dielectric film is made of material having a high dielectric constant.
Claim 5
Dependent Claim
68 words
The method of manufacturing a semiconductor memory device according to claim 1, wherein said step of forming said first and second openings includes the step of forming barrier layers on inner surfaces of said first and second openings, said barrier layers having a function of preventing mutual diffusion of material of said first and second plug electrodes and material of said semiconductor substrate and preventing diffusion of impurity.
Claim 6
Independent Claim
248 words
A method of manufacturing a semiconductor memory device including a memory cell portion and a peripheral circuit portion on a main surface of a semiconductor substrate, said memory cell portion including memory cells for storing information and said peripheral circuit portion including peripheral circuits for controlling an operation of said memory cells, comprising the steps of: forming a first interlayer insulating film to cover said memory cell portion and said peripheral circuit portion; forming in said first interlayer insulating film a first opening to expose a part of said memory cell portion, and a second opening to expose a part of said peripheral circuit portion; forming a conductive layer, which fill said first and second openings, to cover a top surface of said first interlayer insulating film; patterning said conductive layer to form a capacitor lower electrode, which covers said first opening and electrically connected to the part of said memory cell portion, and a pad layer which covers said second opening and electrically connected to the part of said peripheral circuit portion; sequentially forming a capacitor dielectric film and a capacitor upper electrode to cover said capacitor lower electrode; forming a second interlayer insulating film in contact with said first interlayer insulating film and covering said pad layer and said capacitor upper electrode; forming a third opening at said second interlayer insulating film located above said pad layer; and forming an interconnection layer, which is electrically connected to said pad layer, at least in said third opening.
Claim 7
Independent Claim
248 words
A method of manufacturing a semiconductor memory device including a memory cell portion and a peripheral circuit portion on a main surface of a semiconductor substrate, said memory cell portion including memory cells for storing information and said peripheral circuit portion including peripheral circuits for controlling an operation of said memory cells, comprising the steps of: forming a first interlayer insulating film to cover said memory cell portion and said peripheral circuit portion; forming in said first interlayer insulating film a first opening to expose a part of said memory cell portion, and a second opening to expose a part of said peripheral circuit portion; forming a conductive layer, which fill said first and second openings, to cover a top surface of said first interlayer insulating film; patterning said conductive layer to form a capacitor lower electrode, which covers said first opening and electrically connected to the part of said memory cell portion, and a pad layer which covers said second opening and electrically connected to the part of said peripheral circuit portion; sequentially forming a capacitor dielectric film and a capacitor upper electrode to cover said capacitor lower electrode; forming a second interlayer insulating film in contact with said first interlayer insulating film and covering said pad layer and said capacitor upper electrode; forming a third opening at said second interlayer insulating film located above said pad layer; and forming an interconnection layer, which is electrically connected to said pad layer, at least in said third opening.
References Cited (Backward Citations)
US5323343A
Cited
US5612241A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |