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US6177323B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method to form MOSFET with an elevated source/drain for PMOSFET

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1999-04-30
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Granted: 2001-01-23
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Expires: 2019-04-30
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Abstract

Abstract A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer of the first silicon layer and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the sidewalls of the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer. Finally, a thermal process is performed to the semiconductor substrate for diffusing the first type dopants and the second type dopants into the semiconductor substrate.

Inventors

  • 👤 Shye-Lin Wu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 15:42
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01354; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/026; H10D30/60; H10D30/601; H10D64/021; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D30/0212; H10D64/01304; H10D64/01306; H10D64/017; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/1414; H10P32/17; H10P32/171

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 165 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said anti-reflection layer for defining a gate region; removing a second portion of said gate insulator layer to have undercut spaces under said first silicon layer; forming a dielectric layer on said semiconductor substrate, on sidewalls of said first silicon layer, and within said undercut spaces; forming a spacer structure containing first type dopants on sidewalls of said gate region; removing said anti-reflection layer; forming a second silicon layer containing second type dopants on said semiconductor substrate and said first silicon layer; and performing a thermal process to said semiconductor substrate, for diffusing said first type dopants and said second type dopants into said semiconductor substrate.
Claim 2
Independent Claim 165 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said anti-reflection layer for defining a gate region; removing a second portion of said gate insulator layer to have undercut spaces under said first silicon layer; forming a dielectric layer on said semiconductor substrate, on sidewalls of said first silicon layer, and within said undercut spaces; forming a spacer structure containing first type dopants on sidewalls of said gate region; removing said anti-reflection layer; forming a second silicon layer containing second type dopants on said semiconductor substrate and said first silicon layer; and performing a thermal process to said semiconductor substrate, for diffusing said first type dopants and said second type dopants into said semiconductor substrate.
Claim 3
Dependent Claim 14 words
The method of claim 1 , wherein said semiconductor substrate comprises a silicon substrate.
Claim 4
Dependent Claim 39 words
The method of claim 1 , wherein said gate insulator layer comprises a silicon oxide layer which is thermally grown in an oxygen containing ambient from said semiconductor substrate with a thickness of about 15 angstroms to 300 angstroms.
Claim 5
Dependent Claim 27 words
The method of claim 1 , wherein said first silicon layer comprises an undoped polysilicon layer deposited with a thickness of about 300 angstroms to 2000 angstroms.
Claim 6
Dependent Claim 17 words
The method of claim 1 , wherein said anti-reflection layer comprises an nitride layer formed by deposition.
Claim 7
Dependent Claim 82 words
The method of claim 1 , wherein said removing said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer comprises the steps of: forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; and performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer to define said gate region.
Claim 8
Dependent Claim 45 words
The method of claim 1 , wherein said dielectric layer comprises an oxynitride layer which is grown thermally from said semiconductor substrate and said first silicon layer in an nitrogen and oxygen containing ambient, with a thickness between about 5 angstroms to about 100 angstroms.
Claim 9
Dependent Claim 21 words
The method of claim 1 , wherein said spacer structure comprises boron doped glass (BSG), said first type dopants comprising boron.
Claim 10
Dependent Claim 20 words
The method of claim 1 , wherein said second silicon layer comprises doped silicon, said second type dopants comprising boron.
Claim 11
Dependent Claim 19 words
The method of claim 1 , wherein said doped second silicon layer is deposited with a selective epitaxial process.
Claim 12
Dependent Claim 54 words
The method of claim 1 , wherein said thermal process comprises a rapid thermal process (RTP) performed with a temperature between about 700° C. to about 1150° C. in order to diffuse said first type dopants to form an extended source/drain junction; and to diffuse said second type dopants to form a source/drain junction.
Claim 13
Independent Claim 191 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said anti-reflection layer for defining a gate region; removing a second portion of said gate insulator layer to have undercut spaces under said first silicon layer; forming a dielectric layer on said semiconductor substrate, on sidewalls of said first silicon layer, and within said undercut spaces, said dielectric layer comprising an oxynitride film grown thermally from said semiconductor substrate and said first silicon layer in an nitrogen and oxygen containing ambient; forming boron doped glass (BSG) spacer structure on sidewalls of said gate region; removing said anti-reflection layer; forming a boron doped silicon layer over said semiconductor substrate and said first silicon layer; and performing a thermal process to said semiconductor substrate, for diffusing boron dopants in said BSG spacer structure and in said boron doped silicon layer, into said semiconductor substrate.
Claim 14
Independent Claim 191 words
A method of forming a transistor over a semiconductor substrate, said method comprising the steps of: forming a gate insulator layer over said semiconductor substrate; forming a first silicon layer over said gate insulator layer; forming an anti-reflection layer over said first silicon layer; removing a portion of said gate insulator layer, of said first silicon layer, and of said anti-reflection layer for defining a gate region; removing a second portion of said gate insulator layer to have undercut spaces under said first silicon layer; forming a dielectric layer on said semiconductor substrate, on sidewalls of said first silicon layer, and within said undercut spaces, said dielectric layer comprising an oxynitride film grown thermally from said semiconductor substrate and said first silicon layer in an nitrogen and oxygen containing ambient; forming boron doped glass (BSG) spacer structure on sidewalls of said gate region; removing said anti-reflection layer; forming a boron doped silicon layer over said semiconductor substrate and said first silicon layer; and performing a thermal process to said semiconductor substrate, for diffusing boron dopants in said BSG spacer structure and in said boron doped silicon layer, into said semiconductor substrate.
Claim 15
Dependent Claim 14 words
The method of claim 12 , wherein said semiconductor substrate comprises a silicon substrate.
Claim 16
Dependent Claim 39 words
The method of claim 12 , wherein said gate insulator layer comprises a silicon oxide layer which is thermally grown in an oxygen containing ambient from said semiconductor substrate with a thickness of about 15 angstroms to 300 angstroms.
Claim 17
Dependent Claim 27 words
The method of claim 12 , wherein said first silicon layer comprises an undoped polysilicon layer deposited with a thickness of about 300 angstroms to 2000 angstroms.
Claim 18
Dependent Claim 17 words
The method of claim 12 , wherein said anti-reflection layer comprises an nitride layer formed by deposition.
Claim 19
Dependent Claim 82 words
The method of claim 12 , wherein said removing said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer comprises the steps of: forming a photoresist layer over said anti-reflection layer; defining a gate pattern on said photoresist layer; and performing a reactive ion etching (RIE) using said gate pattern as a mask, to remove said portion of gate insulator layer, of said first silicon layer, and of said anti-reflection layer to define said gate region.
Claim 20
Dependent Claim 21 words
The method of claim 12 , wherein said oxynitride film has a thickness between about 5 angstroms to about 100 angstroms.
Claim 21
Dependent Claim 19 words
The method of claim 12 , wherein said boron doped silicon layer is deposited with a selective epitaxial process.
Claim 22
Dependent Claim 61 words
The method of claim 12 , wherein said thermal process comprises a rapid thermal process (RTP) performed with a temperature between about 700° C. to about 1150° C. to diffuse said boron dopants in said BSG spacer structure to form an extended source/drain junction; and to diffuse said boron dopants in said boron doped silicon layer to form a source/drain junction.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-01-23 2004-07-24 2005-01-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-01-23 2008-07-24 2009-01-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-01-23 2012-07-24 2013-01-23 $7700.00 Window Closed / Lapsed

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