US5793059A
Expired / Lapsed
US
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Static random access memory cell and method of fabricating the same
Assignee: SK Hynix Inc
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Filing: 1996-10-28
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Granted: 1998-08-11
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Expires: 2016-10-28
Abstract
Abstract A static random access memory cell having a plurality of active regions defined on a semiconductor substrate, includes a plurality of first bulk transistors having a first common gate electrode and first impurity-doped regions, the first common gate electrode and first impurity-doped regions being formed on a portion of the active regions; a plurality of second bulk transistors spaced from the first bulk transistors, the second bulk transistors including a second common gate electrode and second impurity-doped regions, the second common gate electrode and second impurity-doped regions being formed on a portion of the active regions; and a plurality of thin film transistors formed on the second bulk transistors and including the second common gate electrode and a conductive layer formed above the second common gate electrode, wherein the conductive layer overlaps and is substantially coextensive with the second common gate electrode.
Inventors
- 👤 Joon-Young Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:34
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
142 words
A static random access memory cell including a plurality of active regions defined on a semiconductor substrate, comprising: a plurality of first bulk transistors having a first common gate electrode and first impurity-doped regions, said first common gate electrode and first impurity-doped regions being formed on a portion of the active regions; a plurality of second bulk transistors spaced from said first bulk transistors, said second bulk transistors including a second common gate electrode and second impurity-doped regions, said second common gate electrode and second impurity-doped regions being formed on a portion of the active regions; and a plurality of thin film transistors formed on said second bulk transistors and including said second common gate electrode and a conductive layer formed above said second common gate electrode, wherein said conductive layer overlaps and is substantially coextensive with said second common gate electrode.
Claim 2
Dependent Claim
142 words
A static random access memory cell including a plurality of active regions defined on a semiconductor substrate, comprising: a plurality of first bulk transistors having a first common gate electrode and first impurity-doped regions, said first common gate electrode and first impurity-doped regions being formed on a portion of the active regions; a plurality of second bulk transistors spaced from said first bulk transistors, said second bulk transistors including a second common gate electrode and second impurity-doped regions, said second common gate electrode and second impurity-doped regions being formed on a portion of the active regions; and a plurality of thin film transistors formed on said second bulk transistors and including said second common gate electrode and a conductive layer formed above said second common gate electrode, wherein said conductive layer overlaps and is substantially coextensive with said second common gate electrode.
Claim 3
Dependent Claim
26 words
The static random access memory cell as claimed in claim 1, wherein said conductive layer includes source, drain and channel regions of said thin film transistors.
Claim 4
Dependent Claim
26 words
The static random access memory cell as claimed in claim 1, further comprising: a potential pad which overlaps portions of said first and second bulk transistors.
Claim 5
Dependent Claim
30 words
The static random access memory cell as claimed in claim 3, wherein a portion of said conductive layer formed on said second bulk transistors is overlapped by said potential pad.
Claim 6
Dependent Claim
25 words
The static random access memory cell as claimed in claim 3, further comprising: a transistor connector which overlaps a portion of said second bulk transistors.
Claim 7
Dependent Claim
48 words
The static random access memory cell as claimed in claim 5, wherein a portion of said conductive layer formed on said second bulk transistors, excluding portions of said conductive layer overlapping said potential pad and said transistor connector, serves as a channel region of said thin film, transistors.
Claim 8
Dependent Claim
32 words
The static random access memory cell as claimed in claim 5, further comprising: a cap nitride layer formed on a portion of said second common gate electrode of said second bulk transistors.
Claim 9
Dependent Claim
20 words
Th estatic random access memory cell as claimed ni claim 7, wherein said cap nitride layer contacts said transistor connector.
Claim 10
Dependent Claim
24 words
The static random access memory cell as claimed in claim 7, wherein said cap nitride layer insulates said thin film transistors from each other.
Claim 11
Dependent Claim
46 words
The static random access memory cell, as claimed in claim 1, further comprising: sidewall spacers formed on sides of said second common gate electrode of said second bulk transistors, wherein the height of said sidewall spacers is greater than that of said second common gate electrode.
Claim 12
Dependent Claim
28 words
The static random access memory cell, as claimed in claim 10, wherein said conductive layer is formed above said second common gate electrode and between the sidewall spacers.
Claim 13
Dependent Claim
26 words
The static random access memory cell, as claimed in claim 11, wherein said conductive layer includes source, drain and channel regions of said thin film transistors.
Claim 14
Dependent Claim
36 words
The static random access memory cell, as claimed in claim 1, wherein source, drain and channel regions of said second bulk transistors extend substantially perpendicular to source, drain and channel regions of said thin film transistors.
Claim 15
Dependent Claim
36 words
The static random access memory cell, as claimed in claim 13, wherein said source, drain and channel regions of said thin film transistors are formed in said conductive layer formed above said second common gate electrode.
Claim 16
Dependent Claim
29 words
The static random access memory cell, as claimed in claim 1, wherein a size of said conductive layer substantially corresponds to a size of said second common gate electrode.
Claim 17
Dependent Claim
26 words
The static random access memory cell, as claimed in claim 15, wherein said conductive layer includes source, drain and channel regions of said thin film transistors.
Claim 18
Dependent Claim
29 words
The static random access memory cell, as claimed in claim 1, wherein a shape of said conductive layer substantially corresponds to a shape of said second common gate electrode.
Claim 19
Dependent Claim
26 words
The static random access memory cell, as claimed in claim 17, wherein said conductive layer includes source, drain and channel regions of said thin film transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |