US5348903A
Expired / Lapsed
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Process for fabricating a semiconductor memory cell having thin-film driver transistors overlapping dual wordlines
Assignee: Motorola Solutions Inc
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Filing: 1992-09-03
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Granted: 1994-09-20
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Expires: 2012-09-03
Abstract
Abstract A semiconductor memory cell (10) includes first and second cross-coupled driver transistors (13, 19) each having a source-drain region and a channel region formed in a first thin-film layer (36, 36'). First and second parallel opposed wordlines (20, 22) overlie a single-crystal semiconductor substrate (12) and the channel region (46) of each driver transistor overlies a portion of an adjacent wordline. A portion of the thin-film layer (36, 36') makes contact to the single-crystal semiconductor substrate (12) adjacent to the opposite wordline. The channel and source-drain regions of first and second load transistors (15, 21) are formed in a second thin-film layer (64) which overlies the driver transistors (13, 19). The load transistors (15, 21) are cross-coupled to the driver transistors (13, 19) through common nodes (31, 33).
Inventors
- 👤 James R. Pfiester
- 👤 James D. Hayden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:48
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D86/00; H10D86/201; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
81 words
A process for fabricating a semiconductor memory cell comprising: providing a single-crystal semiconductor substrate; forming first and second parallel opposed wordlines overlying the substrate; and forming first and second cross-coupled thin-film driver transistors overlying the first and second wordlines respectively, wherein each thin-film driver transistor includes a thin-film layer having a source-drain region and a channel region formed therein, and wherein the channel region overlies a portion of the wordline and a portion of the thin-film layer contacts the single-crystal substrate.
Claim 2
Dependent Claim
81 words
A process for fabricating a semiconductor memory cell comprising: providing a single-crystal semiconductor substrate; forming first and second parallel opposed wordlines overlying the substrate; and forming first and second cross-coupled thin-film driver transistors overlying the first and second wordlines respectively, wherein each thin-film driver transistor includes a thin-film layer having a source-drain region and a channel region formed therein, and wherein the channel region overlies a portion of the wordline and a portion of the thin-film layer contacts the single-crystal substrate.
Claim 3
Dependent Claim
59 words
The process of claim 1, wherein the formation of the thin-film layer comprises: depositing a silicon layer to overlie the first and second wordlines; implanting the silicon layer with an element selected from the group consisting of silicon and germanium; annealing the implanted silicon layer to form single-crystal silicon; and etching the single-crystal silicon to form the thin-film layer.
Claim 4
Dependent Claim
23 words
The process of claim 2, wherein the step of annealing the implanted silicon layer comprises exposing the silicon to a coherent light source.
Claim 5
Dependent Claim
28 words
The process of claim 2, wherein the step of depositing a silicon layer comprises depositing a material selected from the group consisting of amorphous silicon and polycrystalline silicon.
Claim 6
Dependent Claim
19 words
The process of claim 1, wherein the formation of the thin-film layer comprises epitaxially growing a single-crystal silicon layer.
Claim 7
Dependent Claim
18 words
The process of claim 1, wherein the formation of the thin-film layer comprises chemical vapor deposition of polysilicon.
Claim 8
Dependent Claim
142 words
A process for fabricating a semiconductor memory cell comprising: providing a single-crystal substrate having an active region and an isolation region; forming a dielectric layer overlying the active region; forming first and second wordlines, the first wordline overlying the active region and the second wordline overlying the isolation region; forming an opening in the dielectric layer adjacent to the first wordline to expose a portion of the single-crystal substrate; forming a single-crystal silicon layer having a first portion overlying the second wordline and a second portion in contact with the single-crystal substrate through the opening in the dielectric layer and a third portion overlying a portion of the first wordline; forming a driver-gate electrode overlying the first portion of the single-crystal silicon layer; and doping the single-crystal silicon layer to form source and drain regions on opposing sides of the driver-gate electrode.
Claim 9
Dependent Claim
142 words
A process for fabricating a semiconductor memory cell comprising: providing a single-crystal substrate having an active region and an isolation region; forming a dielectric layer overlying the active region; forming first and second wordlines, the first wordline overlying the active region and the second wordline overlying the isolation region; forming an opening in the dielectric layer adjacent to the first wordline to expose a portion of the single-crystal substrate; forming a single-crystal silicon layer having a first portion overlying the second wordline and a second portion in contact with the single-crystal substrate through the opening in the dielectric layer and a third portion overlying a portion of the first wordline; forming a driver-gate electrode overlying the first portion of the single-crystal silicon layer; and doping the single-crystal silicon layer to form source and drain regions on opposing sides of the driver-gate electrode.
Claim 10
Dependent Claim
60 words
The process of claim 7, wherein the step of forming a single-crystal silicon layer comprises: depositing a layer of silicon to overlie the substrate; implanting the silicon layer with an element selected from the group consisting of silicon and germanium; annealing the implanted silicon layer to form single-crystal silicon; and etching the single-crystal silicon to form a patterned thin-film layer.
Claim 11
Dependent Claim
28 words
The process of claim 8, wherein the step of depositing a silicon layer comprises depositing a material selected from the group consisting of amorphous silicon and polycrystalline silicon.
Claim 12
Dependent Claim
23 words
The process of claim 8, wherein the step of annealing the implanted silicon layer comprises exposing the silicon to a coherent light source.
Claim 13
Dependent Claim
34 words
The process of claim 7, wherein the step of forming a single-crystal silicon layer comprises epitaxially growing a single-crystal silicon layer using the exposed portion of the single crystal substrate as a nucleation site.
Claim 14
Dependent Claim
96 words
The process of claim 7 further comprising the steps of: forming a polysilicon interconnect layer having a first portion overlying and electrically insulated from the single-crystal silicon layer, and having a second portion overlying a portion of the first wordline and electrically insulated from the first wordline, wherein the second portion is separate from the first portion; and forming a thin-film transistor overlying and insulated from the second wordline, the thin-film transistor having a second gate electrode overlying a channel region, wherein the second gate electrode and the channel region are aligned with the driver-gate electrode.
References Cited (Backward Citations)
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