US5145799A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked capacitor SRAM cell
Assignee: Texas Instruments Inc
•
Filing: 1991-01-30
•
Granted: 1992-09-08
•
Expires: 2011-01-30
Abstract
Abstract This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.
Inventors
- 👤 Mark S. Rodder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:47
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10B; H10B10/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
192 words
A method of forming an SRAM cell, the cell having first and second NMOS drive transistors, and first and second PMOS load transistors; said method comprising: a. forming a first bottom capacitor plate over a gate of said second drive transistor and second bottom capacitor plate over a gate of said first drive transistor; b. electrically connecting said first bottom capacitor plate to said second drive transistors gate; c. electrically connecting said second bottom capacitor plate to said first drive transistor gate; d. forming dielectric layer over said first and second bottom capacitor plates; e. forming first and second top capacitor plates over said dielectric layer, with said first top capacitor plate forming a gate of said first load transistor and being over said first bottom capacitor plate, and said second top capacitor plate forming a gate of said second load transistor and being over said second bottom capacitor plate; f. electrically connecting said first top capacitor plate to said first drive transistor gate; g. electrically connecting said second top capacitor plate to said second drive transistor gate; and h. forming PMOS channel films over said first and second top capacitor plates.
Claim 2
Independent Claim
192 words
A method of forming an SRAM cell, the cell having first and second NMOS drive transistors, and first and second PMOS load transistors; said method comprising: a. forming a first bottom capacitor plate over a gate of said second drive transistor and second bottom capacitor plate over a gate of said first drive transistor; b. electrically connecting said first bottom capacitor plate to said second drive transistors gate; c. electrically connecting said second bottom capacitor plate to said first drive transistor gate; d. forming dielectric layer over said first and second bottom capacitor plates; e. forming first and second top capacitor plates over said dielectric layer, with said first top capacitor plate forming a gate of said first load transistor and being over said first bottom capacitor plate, and said second top capacitor plate forming a gate of said second load transistor and being over said second bottom capacitor plate; f. electrically connecting said first top capacitor plate to said first drive transistor gate; g. electrically connecting said second top capacitor plate to said second drive transistor gate; and h. forming PMOS channel films over said first and second top capacitor plates.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein said first and second bottom capacitor plates are fabricated from silicon.
Claim 4
Dependent Claim
17 words
The method of claim 1, wherein said first and second top capacitor plates are fabricated from silicon.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein said first and second bottom capacitor plates are over gate sidewalls of said drive transistors.
Claim 6
Dependent Claim
21 words
The method of claim 1, wherein said first and second top capacitor plates are over gate sidewalls of said drive transistors.
Claim 7
Dependent Claim
11 words
The method of claim 1, wherein said dielectric layer is oxide.
Claim 8
Dependent Claim
11 words
The method of claim 1, wherein said dielectric layer is nitride.
Claim 9
Dependent Claim
12 words
The method of claim 1, wherein said dielectric layer is tantalum oxide.
Claim 10
Dependent Claim
13 words
The method of claim 1, wherein said dielectric layer contains oxide and nitride.
References Cited (Backward Citations)
US4541006A
Cited
US4907057A
Cited
US4890141A
Cited
US4803534A
Cited
US4794561A
Cited
JPS6422057A
Cited
US5001539A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-08 | 1996-03-09 | 1996-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-08 | 2000-03-09 | 2000-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-08 | 2004-03-09 | 2004-09-08 | $7700.00 | Window Closed / Lapsed |