US5516715A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing static random access memory device having thin film transister loads
Assignee: Fujitsu Ltd
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Filing: 1994-10-27
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Granted: 1996-05-14
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Expires: 2014-10-27
Abstract
Abstract A method of producing a semiconductor memory cell. The memory cell includes two transfer transistors, two driver transistors, two thin film transistor loads and two word lines respectively coupled to gate electrodes of the transfer transistors. The method includes (a) forming a field insulator layer on a semiconductor substrate, (b) forming a gate insulator layer, (c) forming a gate electrode of a driver transistor by forming and patterning a first conductor layer, (d) forming a first insulator layer on the first conductor layer after impurity regions are formed in the semiconductor substrate, (e) forming and patterning a second conductor layer on the first insulator layer, (f) forming a second insulator layer on the second conductor layer, (g) forming and patterning a third conductor layer on the second insulator layer, (h) forming a third insulator layer on the third conductor layer, (i) forming a contact hole which extends from the top surface of the third insulator layer to the top surface of the first conductor layer, the contact hole extending through the second conductor layer and the third conductor layer, and (j) forming a fourth conductor layer which extends into the contact hole to make contact with the first conductor layer, the second conductor layer and the third conductor layer.
Inventors
- 👤 Kazuo Itabashi
- 👤 Taiji Ema
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:19
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
285 words
A method of producing a semiconductor memory device comprising a memory cell formed on a semiconductor substrate, the memory cell comprising two transfer transistors which each have a gate electrode, two driver transistors, two thin film transistor loads and two word lines respectively coupled to gate electrodes of the transfer transistors, the method comprising: forming a field insulator layer on the semiconductor substrate; forming a gate insulator layer on the semiconductor substrate after forming the field insulator layer; forming a gate electrode of a driver transistor by forming and patterning a first conductor layer on the semiconductor substrate, the first conductor layer having a top surface; forming a first insulator layer on the top surface of the first conductor layer after impurity regions are formed in the semiconductor substrate, using the field insulator layer and the first conductor layer as masks; forming and patterning a second conductor layer on the first insulator layer; forming a second insulator layer on the second conductor layer; forming and patterning a third conductor layer on the second insulator layer; forming a third insulator layer on the third conductor layer, the third insulator having a top surface; forming a contact hole which extends from the top surface of the third insulator layer to the top surface of the first conductor layer, the contact hole extending through the second conductor layer and the third conductor layer to form side surfaces in the second conductor layer and the third conductor layer; and forming a fourth conductor layer which extends into the contact hole to make contact with the top surface of the first conductor layer, the side surface of the second conductor layer and the side surface of the third conductor layer.
Claim 2
Independent Claim
285 words
A method of producing a semiconductor memory device comprising a memory cell formed on a semiconductor substrate, the memory cell comprising two transfer transistors which each have a gate electrode, two driver transistors, two thin film transistor loads and two word lines respectively coupled to gate electrodes of the transfer transistors, the method comprising: forming a field insulator layer on the semiconductor substrate; forming a gate insulator layer on the semiconductor substrate after forming the field insulator layer; forming a gate electrode of a driver transistor by forming and patterning a first conductor layer on the semiconductor substrate, the first conductor layer having a top surface; forming a first insulator layer on the top surface of the first conductor layer after impurity regions are formed in the semiconductor substrate, using the field insulator layer and the first conductor layer as masks; forming and patterning a second conductor layer on the first insulator layer; forming a second insulator layer on the second conductor layer; forming and patterning a third conductor layer on the second insulator layer; forming a third insulator layer on the third conductor layer, the third insulator having a top surface; forming a contact hole which extends from the top surface of the third insulator layer to the top surface of the first conductor layer, the contact hole extending through the second conductor layer and the third conductor layer to form side surfaces in the second conductor layer and the third conductor layer; and forming a fourth conductor layer which extends into the contact hole to make contact with the top surface of the first conductor layer, the side surface of the second conductor layer and the side surface of the third conductor layer.
Claim 3
Dependent Claim
105 words
The method as claimed in claim 1, wherein the second conductor layer and the third conductor layer are made of polysilicon, the first insulator layer, the second insulator layer and the third insulator layer are made of SiO 2 , and the step of forming a contact hole comprises: performing a reactive ion etching processes using CHF 3 /He as an etching gas to remove the first insulator layer, the second insulator layer and the third insulator layer; and performing a reactive ion etching process using CCl 4 /O 2 as an etching gas to remove the second conductor layer and the third conductor layer.
Claim 4
Dependent Claim
62 words
The method as claimed in claim 1, wherein the step of forming a gate electrode comprises forming the first conductor layer to be made of a first layer formed on the semiconductor substrate and a second layer formed on the first layer, the second layer being made of a material selected from the group consisting of refractory metals and refractory metal silicides.
Claim 5
Dependent Claim
102 words
The method as claimed in claim 3, wherein the second conductor layer and the third conductor layer are made of polysilicon, the first insulator layer, the second insulator layer and the third insulator layer are made of SiO 2 , and the step of forming a contact hole comprises: performing a reactive ion etching process using CHF 3 /He as an etching gas to remove the first insulator layer, the second insulator layer and the third insulator layer; and performing a reactive ion etching process using HBr/Ar as an etching gas to remove the second conductor layer and the third conductor layer.
Claim 6
Dependent Claim
34 words
The method as claimed in claim 3, wherein the step of forming a contact hole comprises: performing an over-etching to form a second hole, so that etching residue within the second hole is removed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-14 | 1999-11-13 | 2000-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-14 | 2003-11-13 | 2004-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-14 | 2007-11-13 | 2008-05-14 | $7700.00 | Window Closed / Lapsed |