EP0443549A2
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EP
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Semiconductor memory
Assignee: Sony Corp
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Filing: 1991-02-20
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Granted: —
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Expires: 2011-02-20
Abstract
Abstract A pair of load transistors (Q3, Q4) of a flip-flop circuit constituting a memory cell consist of thin film transistors, and channel regions (19, 22) of the pair of load transistors (Q3, Q4) overlap drain regions (20, 23) of the load transistors (Q3, Q4) through a gate insulating film (21). For this reason, a channel length of the load transistors (Q3, Q4) can be sufficiently increased, and a leakage current of the load transistor (Q3, Q4) can be reduced. <IMAGE>
Inventors
- 👤 Ikuo Kanagawa Yoshihara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 19:36
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
100 words
A semiconductor memory comprising a memory cell having a flip-flop circuit consisting of a pair of driver transistors (Q₁, Q₂) of a first conductivity type channel and a pair of load transistors (Q₃, Q₄) of a second conductivity type channel, and a pair of access transistors (Q₅, Q₆), wherein said pair of load transistors (Q₃, Q₄) of the second conductivity type channel are formed by semiconductor thin films such that channel regions (19, 22) and drain regions (20, 23) of said pair of load transistors (Q₃, Q₄) of the second conductivity type channel overlap through a gate insulating film (21).
Claim 2
Dependent Claim
45 words
A semi conductor memory according to claim 1, wherein source regions of said pair of load transistors (Q₃, Q₄) of the second conductivity type channel extend in opposite directions and are connected to power source lines (14, 18) between which the memory cell is located.
Claim 3
Dependent Claim
57 words
A semiconductor memory according to claim 1 or 2, wherein said pair of driver transistors (Q₁, Q₂) of the first conductivity type channel are formed by semiconductor thin films such that channel regions and drain regions of said pair of driver transistors (Q₁, Q₂) of the first conductivity type channel overlap through a gate insulating film (4).
Claim 4
Dependent Claim
53 words
A semiconductur memory according to anyone of claims 1 to 3, wherein widths of said semiconductor thin films of said pair of load transistors (Q₃, Q₄) of the second conductivity type channel are larger at a portion of said drain region (20, 23) than at a portion of said channel region (19, 20).
Claim 5
Dependent Claim
98 words
A semiconductor memory comprising a memory cell having a flip-flop circuit consisting of a pair of driver transistors (Q₁, Q₂) of a first conductivity type channel and a pair of load transistors (Q₃, Q₄) of a second conductivity type channel, and a pair of access transistors (Q₅, Q₆), wherein said pair of load transistors (Q₃, Q₄) of the second conductivity type channel are formed by semiconductor thin films and gate electrodes (20, 23) of said pair of load transistors (Q₃, Q₄) of the second conductivity type channel are formed by semiconductor thin films of the second conductivity type.
References Cited (Backward Citations)
No citation records indexed.
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