US6173386B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Parallel processor with debug capability
Assignee: Cisco Technology Inc
•
Filing: 1998-12-14
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Granted: 2001-01-09
•
Expires: 2018-12-14
Abstract
Abstract A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.
Inventors
- 👤 Kenneth Michael Key
- 👤 Michael L. Wright
- 👤 Darren Kerr
- 👤 William E. Jennings
- 👤 Scott Nellenbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:50
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
172 words
A parallel processor, comprising: a plurality of parallel processing elements, each of the elements comprising a respective central processing unit; a fault signal generator for generating a global fault signal for being supplied to the elements to trigger all of said elements to enter a debug mode of operation, said generator generating said fault signal in response to one of a debug enable signal supplied to said processor from a source external to said processor and a global exception signal, the debug mode of operation being a single step mode of operation, the global fault signal indicating that an error condition has occurred in one of the elements, the processor also comprising an exception handling mechanism that stores an exception identification value that uniquely identifies the one of the elements in which the error condition has occurred, the value stored in the mechanism being readable by a processing system external to the processor, the mechanism also generating the global exception signal in response to another exception signal generated by the one element.
Claim 2
Dependent Claim
172 words
A parallel processor, comprising: a plurality of parallel processing elements, each of the elements comprising a respective central processing unit; a fault signal generator for generating a global fault signal for being supplied to the elements to trigger all of said elements to enter a debug mode of operation, said generator generating said fault signal in response to one of a debug enable signal supplied to said processor from a source external to said processor and a global exception signal, the debug mode of operation being a single step mode of operation, the global fault signal indicating that an error condition has occurred in one of the elements, the processor also comprising an exception handling mechanism that stores an exception identification value that uniquely identifies the one of the elements in which the error condition has occurred, the value stored in the mechanism being readable by a processing system external to the processor, the mechanism also generating the global exception signal in response to another exception signal generated by the one element.
Claim 3
Dependent Claim
20 words
A parallel processor according to claim 1 , further comprising, for receiving said debug enable signal, an external trigger pin.
Claim 4
Dependent Claim
52 words
A parallel processor according to claim 1 , further comprising, a register and other circuitry, the register being for storing a global debug enable value for being supplied to the other circuitry, the other circuitry being configured to cause generation of the global fault signal in response to receipt of the value.
Claim 5
Dependent Claim
78 words
A parallel processor according to claim 1 , further comprising a step mode run enable register, and wherein said processing elements are configured such that, when said processing elements are in said debug mode, said processing elements halt respective processing operations until a value contained in said step mode run enable register is changed, and after said value is changed, said processing elements execute only respective processing that consumes only a single clock cycle, and thereafter halt again.
Claim 6
Dependent Claim
52 words
A parallel processor according to claim 1 , wherein said parallel processor further comprises a buffer for providing data from an external data source to said processing elements, said buffer being configured to enter, upon command, respective debug mode of operation, the respective debug mode being a single step mode of operation.
Claim 7
Dependent Claim
90 words
A parallel processor according to claim 1 , wherein said parallel processor further comprises a buffer for receiving data from an external data source and for supplying the data to the processing elements, the buffer being configured to enter a respective debug mode of operation upon command, the respective debug mode being an operation mode wherein execution of a processing phase of the data by a next active group of processing elements is permitted, and after the phase has completed, processing of the data by the processing elements is halted.
Claim 8
Dependent Claim
156 words
A parallel processor, comprising: a plurality of parallel processing elements, each of the elements comprising a respective central processing unit; and a debug triggering signal generator for generating a debug triggering signal for being supplied to at least one of said processing elements to cause the at least one of the processing elements to enter a local debug mode of operation, said generator generating said signal in response to at least a debug acknowledgment signal generated by another of said processing elements indicating that said another of said processing elements has entered said local debug mode, said debug mode of operation being a single step mode of operation, the generator generating the debug triggering signal based upon a debug request mask value stored in a mask register, the value specifying which of the processing elements is to enter the local debug mode when the debug acknowledge signal is generated by the another of the processing elements.
Claim 9
Dependent Claim
156 words
A parallel processor, comprising: a plurality of parallel processing elements, each of the elements comprising a respective central processing unit; and a debug triggering signal generator for generating a debug triggering signal for being supplied to at least one of said processing elements to cause the at least one of the processing elements to enter a local debug mode of operation, said generator generating said signal in response to at least a debug acknowledgment signal generated by another of said processing elements indicating that said another of said processing elements has entered said local debug mode, said debug mode of operation being a single step mode of operation, the generator generating the debug triggering signal based upon a debug request mask value stored in a mask register, the value specifying which of the processing elements is to enter the local debug mode when the debug acknowledge signal is generated by the another of the processing elements.
Claim 10
Dependent Claim
61 words
A parallel processor according to claim 7 , wherein said another of said processing elements comprises a circuit for causing said another of said processing elements to enter said debug mode and generating said debug acknowledgment signal when a program counter of said another of said processing elements points to an instruction whose address corresponds to at least one debug breakpoint.
Claim 11
Dependent Claim
38 words
A parallel processor according to claim 8 , further comprising, a breakpoint detection circuit configured to detect when a memory location whose address corresponds to a data breakpoint has been accessed by said another of said processing elements.
Claim 12
Dependent Claim
83 words
A parallel processor according to claim 7 , further comprising a step mode run enable register, and wherein said processing elements are configured such that, when said processing elements are in said debug mode, said processing elements halt respective processing operations until a value contained in said [a] step mode run enable register is changed, and after said value is changed, the processing elements in the debug mode execute only respective processing that consumes only a single clock cycle, and thereafter halt again.
Claim 13
Dependent Claim
51 words
A parallel processor according to claim 7 , wherein said parallel processor further comprises a buffer for providing data from an external data source to said processing elements, said buffer being configured to enter, upon command, a respective debug mode, the respective debug mode being a single step mode of operation.
Claim 14
Dependent Claim
90 words
A parallel processor according to claim 7 , wherein said parallel processor further comprises a buffer for receiving data from an external data source and for supplying the data to the processing elements, the buffer being configured to enter a respective debug mode of operation upon command, the respective debug mode being an operation mode wherein execution of a processing phase of the data by a next active group of processing elements is permitted, and after the phase has completed, processing of the data by the processing elements is halted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-09 | 2004-07-10 | 2005-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-09 | 2008-07-10 | 2009-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-09 | 2012-07-10 | 2013-01-09 | $7700.00 | Window Closed / Lapsed |