US4791641A
Expired / Lapsed
US
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Parallel processor error checking
Assignee: Thinking Machines Corp
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Filing: 1986-09-15
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Granted: 1988-12-13
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Expires: 2006-09-15
Abstract
Abstract A system for error correction in the reading and writing of data to memory in a multiprocessor environment such as a parallel processor. The data written to and read from memory for each processor is channeled through a single error correcting system which effectively treats the data for plural memories associated with plural processors as a single data word and generates a single error correcting code for that combined data word. By applying a single error correcting methodology to a plurality of memories and associated processors, far greater efficiency is achieved in the parallel processor environment. The read and write operations for the plural memories must be accomplished substantially simultaneously in order that the read and write operations can be treated as acting on a single word and a single error correcting code generated. This ideally suits the system for use in parallel processor environments where the processing function is distributed over a multiplicity of processors and associated memories, acting in parallel.
Inventors
- 👤 W. Daniel Hillis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:55
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1004; G06F11/1008; G06F11/1048
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
123 words
An error correcting system for use with a plurality of digital processors and associated digital memory areas comprising: a plurality of digital processors; a digital memory area for data storage and retrieval; a control interface for communicating data between said plurality of digital processors and said digital memory area in a unitary digital word comprising portions from plural ones of said plural processors and for generating a unitary error correcting code as a function of said unitary digital word being written into said memory area from said plurality of processors and for providing error detection and correction as a function said unitary error correction code on said unitary digital word read from said memory area to corresponding ones of said plurality of processors.
Claim 2
Dependent Claim
123 words
An error correcting system for use with a plurality of digital processors and associated digital memory areas comprising: a plurality of digital processors; a digital memory area for data storage and retrieval; a control interface for communicating data between said plurality of digital processors and said digital memory area in a unitary digital word comprising portions from plural ones of said plural processors and for generating a unitary error correcting code as a function of said unitary digital word being written into said memory area from said plurality of processors and for providing error detection and correction as a function said unitary error correction code on said unitary digital word read from said memory area to corresponding ones of said plurality of processors.
Claim 3
Dependent Claim
37 words
The system of claim 1 further comprising system timing and control means for providing simultaneous writing and reading of the portions of said unitary digital word in said memory area corresponding to a unitary error correcting code.
Claim 4
Dependent Claim
23 words
The system of claim 1 further including external digital processing means for controlling said plurality of processors to provide a parallel processing relationship.
Claim 5
Dependent Claim
27 words
The system of claim 1 wherein each of said plurality of memory areas is associated with a corresponding one of each of said plurality of data processors.
Claim 6
Dependent Claim
47 words
The system of claim 1 wherein said plural memory areas comprise corresponding segments of a single memory address, one segment of said memory address being utilized for each error correcting code corresponding to the unitary digital word as a whole in plural other segments of said address.
Claim 7
Dependent Claim
15 words
The system of claim 1 wherein said error correcting code comprises a single parity bit.
Claim 8
Dependent Claim
15 words
The system of claim 1 wherein said error correcting code comprises a plurality of bits.
Claim 9
Dependent Claim
96 words
An error correcting method for use with a plurality of digital processors and associated digital memory area comprising: writing and reading a unitary digital word having portions from and to plural ones of said processors into and out of a digital memory area; generating a unitary error correcting code as a function of said unitary digital word being written into said memory area; detecting errors corresponding to said written unitary digital word as read from said of memory area; correcting detected errors as a function of said unitary correcting code in the read unitary digital word.
Claim 10
Dependent Claim
96 words
An error correcting method for use with a plurality of digital processors and associated digital memory area comprising: writing and reading a unitary digital word having portions from and to plural ones of said processors into and out of a digital memory area; generating a unitary error correcting code as a function of said unitary digital word being written into said memory area; detecting errors corresponding to said written unitary digital word as read from said of memory area; correcting detected errors as a function of said unitary correcting code in the read unitary digital word.
Claim 11
Dependent Claim
28 words
The method of claim 8 further including providing simultaneous wirting and reading of said unitary digital word in said memory area corresponding to a unitary error correcting code.
Claim 12
Dependent Claim
16 words
The method of claim 8 further including associating said plurality of processors to provide parallel processing.
Claim 13
Dependent Claim
29 words
The method of claim 8 wherein said memory area comprises a plurality of memory areas each associated with a corresponding one of each of said plurality of data processors.
Claim 14
Dependent Claim
46 words
The method of claim 11 wherein said plural memory areas comprise corresponding segments of a single memory address, one segment of said memory address being utilized for each error correcting code corresponding to the unitary digital word as a whole in other segments of said address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-13 | 1992-06-13 | 1992-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-13 | 1996-06-13 | 1996-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-13 | 2000-06-13 | 2000-12-13 | $7700.00 | Window Closed / Lapsed |