Method and system for supporting speculative execution using a speculative look-aside table

Claim 2

In a processor, logic for supporting speculative execution comprising: a speculative look aside table including a plurality of entries for storing data indicating whether an exception is being deferred; a predicate register file including a plurality of entries operable to store a predicate for controlling execution of one or more operations and a label representing an index into the speculative look aside table; a predicate decoder operable to read a predicate and to locate a corresponding entry in the predicate register file; control logic operable to read a predicate value and a label from the corresponding entry in the predicate register file; and a label decoder communicative with the control logic, the label decoder operable to receive the label from the control logic and operable to locate a corresponding entry in the speculative look aside table.

Claim 3

The logic of claim 1 wherein the plurality of entries in the predicate register file include a first bit field for storing a 1 bit predicate, and an n-bit label for storing the index into the speculative look aside table, where n is an integer greater than or equal to two.

Claim 4

The logic of claim 1 wherein the processor includes a decode stage in which an operation is decoded, a read stage in which one or more operands of the operation are read, an execute stage in which the operation is executed, and a write stage in which a result of the operation is written to a target register; and wherein the predicate decoder is operable to control reading of the corresponding entry in the predicate register file at the read stage to determine whether the operation is speculative.

Claim 5

The logic of claim 1 wherein the processor includes a decode stage in which an operation is decoded, a read stage in which one or more operands of the operation are read, an execute stage in which the operation is executed, and a write stage in which a result of the operation is written to a target register; wherein the control logic is operable to issue the label from the corresponding entry in the predicate register file to the label decoder during the execute stage; and wherein the logic includes halt logic operable to read the corresponding entry in the speculative look aside table during the execute stage, and operable to halt execution of the operation when a poison bit is set in the corresponding entry in the speculative look aside table.

Claim 6

The logic of claim 1 further including check logic communicative with the speculative look aside table, the check logic operable to read the corresponding entry in the speculative look aside table and operable to initiate recovery from an exception when a poison bit is set.

Claim 7

The logic of claim 1 further including a second label decoder, the second label decoder operable to control writing a poison bit to the corresponding entry in the speculative look aside table.

Claim 8

The logic of claim 6 wherein the processor includes a decode stage in which an operation is decoded, a read stage in which one or more operands of the operation are read, an execute stage in which the operation is executed, and a write stage in which a result of the operation is written to a target register; and wherein the second label decoder is operable to control writing the poison bit to the corresponding entry in the speculative look aside table during the write stage.

Claim 9

The logic of claim 1 further including a second predicate decoder operable to control writing of results of an operation on a predicate, including a label, to one or more entries in the predicate register file.

Claim 10

The logic of claim 8 wherein the processor includes a decode stage in which an operation is decoded, a read stage in which one or more operands of the operation are read, an execute stage in which the operation is executed, and a write stage in which a result of the operation is written to a target register; and wherein the second predicate decoder controls the writing of the results of the operation on the predicate during the write stage.

Claim 11

The logic of claim 1 wherein the processor includes a functional unit, and the functional unit has a label operator to attach a label to a predicate in the predicate register file.

Claim 12

The logic of claim 1 wherein the processor includes a functional unit, and the functional unit has check logic to determine whether an entry in the speculative look aside table corresponding to a specified label includes a poison bit.

Claim 13

The logic of claim 1 wherein the plurality of entries in the speculative look aside table include a field for storing a poison bit indicating whether an exception is being deferred.

Claim 14

The logic of claim 1 wherein the plurality of entries in the speculative look aside table include a field for storing one or more status bits used to control processing of a deferred exception.

Claim 15

The logic of claim 13 wherein the status bits include status bits to control the processing of a deferred exception for a floating point operation.

Claim 16

The logic of claim 13 wherein the plurality of entries in the speculative look aside table include an address field for storing a memory location of recovery code.

Claim 19

The method of claim 16 further including: reading the label to determine whether the operation is a speculative operation; setting a poison bit in the entry of the speculative look aside table corresponding to the label when the operation is speculative and generates an exception.

Claim 20

The method of claim 16 further including: decoding the operation to determine whether the operation has a predicate target; computing results of the operation; and writing the results of the operation including the label to an entry in a predicate register file corresponding to the predicate target.

Claim 21

The method of claim 16 further including: in an explicit check operation, determining whether the entry corresponding to a label specified in the explicit check operation is storing a flag indicating that an exception has been deferred; and when the flag is detected, branching to re-execution code including operations qualified with predicates having the label specified in the check operation.

Claim 22

In a processor having a decode stage in which an operation is decoded, a read stage in which one or more operands of the operation are read, an execute stage in which the operation is executed, and a write stage in which a result of the operation is written to a target register, logic for supporting speculative execution comprising: a speculative look aside table including a plurality of entries for storing a poison bit indicating whether an exception is being deferred; a predicate register file including a plurality of entries operable to store a predicate value for controlling execution of one or more operations and a label representing an index into the speculative look aside table; a first predicate decoder operable to read a predicate and to locate a corresponding entry in the predicate file during the read stage of the processor; a second predicate decoder operable to control writing of results of an operation on a predicate, including a label, to one or more entries in the predicate file; control logic operable to read a predicate value and a label from the corresponding entry in the predicate file and to issue the label to a first label decoder; the first label decoder communicative with the control logic to receive the label from the control logic, and operable to read a corresponding entry in the speculative look aside table; and a second label decoder communicative with the speculative look aside table, the second label decoder operable to control writing a poison bit to the corresponding entry in the speculative look aside table.

Claim 23

In a processor having a decode stage in which an operation is decoded, a read stage in which one or more operands of the operation are read, an execute stage in which the operation is executed, and a write stage in which a result of the operation is written to a target register, logic for supporting speculative execution comprising: a speculative look aside table including a plurality of entries for storing a poison bit indicating whether an exception is being deferred; a predicate register file including a plurality of entries operable to store a predicate value for controlling execution of one or more operations and a label representing an index into the speculative look aside table; a first predicate decoder operable to read a predicate and to locate a corresponding entry in the predicate file during the read stage of the processor; a second predicate decoder operable to control writing of results of an operation on a predicate, including a label, to one or more entries in the predicate file; control logic operable to read a predicate value and a label from the corresponding entry in the predicate file and to issue the label to a first label decoder; the first label decoder communicative with the control logic to receive the label from the control logic, and operable to read a corresponding entry in the speculative look aside table; and a second label decoder communicative with the speculative look aside table, the second label decoder operable to control writing a poison bit to the corresponding entry in the speculative look aside table.