US5404562A
Expired / Lapsed
US
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Massively parallel processor including queue-based message delivery system
Assignee: RTPC Corp
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Filing: 1993-10-01
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Granted: 1995-04-04
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Expires: 2013-10-01
Abstract
Abstract A massively parallel computer system including a plurality of processing nodes under control of a system controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises at least one processor, a memory, and a router node connected to the communications links for transferring in a series of message transfer cycles messages over the communications links. The controller enables each processing node to establish a message queue in its memory. The controller further enables storage of messages received by the processing nodes for their respective processors during a message transfer cycle to be stored in the message queue.
Inventors
- 👤 Steven K. Heller
- 👤 Kevin B. Oliveau
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:52
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17381
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
244 words
A massively parallel computer system comprising: A. a plurality of processing nodes, each processing node including at least one processor and a memory, each processing node receiving processor control signals for performing processing operations in connection with data in said memory and for generating and receiving messages; B. a communications network including a plurality of router nodes interconnected by communications links, at least some of the router nodes being connected to said processing nodes, the router nodes being responsive to routing control signals to receive messages from said processing nodes and transfer the messages over the communications links to said processing nodes which are to receive the messages; and C. a controller connected to all of said processing nodes and said router nodes for i. generating processor control signals for transmission to all of said processing nodes in parallel to control said router nodes to: (a) establish in parallel a message queue in the processing nodes+ respective memories; (b) generate messages in parallel for transmission to said router nodes; (c) receive messages in parallel from said router nodes; and (d) append in parallel said received messages to the processing nodes' respective message queues; and ii. generating routing control signals to enable said router nodes to transfer messages generated by the processing nodes over said communications links, the messages to be received by the messages' respective destination processing nodes; thereby to enable the processing nodes to, in parallel, append respective successively-received messages to respective queues.
Claim 2
Dependent Claim
244 words
A massively parallel computer system comprising: A. a plurality of processing nodes, each processing node including at least one processor and a memory, each processing node receiving processor control signals for performing processing operations in connection with data in said memory and for generating and receiving messages; B. a communications network including a plurality of router nodes interconnected by communications links, at least some of the router nodes being connected to said processing nodes, the router nodes being responsive to routing control signals to receive messages from said processing nodes and transfer the messages over the communications links to said processing nodes which are to receive the messages; and C. a controller connected to all of said processing nodes and said router nodes for i. generating processor control signals for transmission to all of said processing nodes in parallel to control said router nodes to: (a) establish in parallel a message queue in the processing nodes+ respective memories; (b) generate messages in parallel for transmission to said router nodes; (c) receive messages in parallel from said router nodes; and (d) append in parallel said received messages to the processing nodes' respective message queues; and ii. generating routing control signals to enable said router nodes to transfer messages generated by the processing nodes over said communications links, the messages to be received by the messages' respective destination processing nodes; thereby to enable the processing nodes to, in parallel, append respective successively-received messages to respective queues.
Claim 3
Dependent Claim
55 words
A system as defined in claim 1 in which the message queue in each processing node includes a queue count portion for storing a message count, said controller generating processor control signals for enabling said processing nodes to increment the message count in their respective queue count portions in response to receipt of a message.
Claim 4
Dependent Claim
75 words
A system as defined in claim 2 in which each processing node includes a plurality of processors, and in which each message identifies a processor, said controller enabling each queue count portion to include a plurality of count slots, each count slot being associated with a processor, said controller generating processor control signals enabling the processors to, in parallel in response to receipt of a message, increment the message count in their respective count slot.
Claim 5
Dependent Claim
48 words
A system as defined in claim 1 in which, in the message queue in each processing node, a queue slot portion includes a plurality of queue slots, said controller generating processor control signals enabling received messages to be stored in successive queue slots in said queue slot portion.
Claim 6
Dependent Claim
56 words
A system as defined in claim 4 in which the message queue in each processing node further includes a queue count portion for storing a message count, said controller generating processor control signals enabling the processors of processing nodes which have received messages to, in parallel, increment the message counts in said respective queue count portions.
Claim 7
Dependent Claim
48 words
A system as defined in claim 5 in which the controller generates router control signals that enable the router nodes to, in parallel, use the message count in the queue count portion to identify a slot in the respective message queue in which a received message is stored.
Claim 8
Dependent Claim
75 words
A system as defined in claim 6 in which each processing node further includes a maximum slot count value identifying a maximum number of queue slots in the processing node's message queue, the controller generating processor control signals enabling said processor nodes to, in parallel in response to receipt of a message, further use the maximum slot count value in identifying a slot in the message queue in which a respective received message is stored.
Claim 9
Dependent Claim
65 words
A system as defined in claim 7 in which the controller generates processor control signals to enable said processor nodes to, in parallel in response to receipt of a message, use a value corresponding to a minimum of the respective message count and the respective maximum slot count value to identify a slot in the message queue in which a respective received message is stored.
Claim 10
Dependent Claim
81 words
A system as defined in claim 5 in which each processing node includes a plurality of processors, and in which each message identifies a processor, each queue count portion further including a plurality of count slots, each count slot being associated with a processor, said controller generating processor control signals enabling the processor nodes to, in parallel in response to receipt of, respective messages increment the message count in the count slot associated with the processors identified by the received messages.
Claim 11
Dependent Claim
84 words
A system as defined in claim 9 in which each queue slot also includes a plurality of processor slot, each processor slot in each queue slot being associated with a processor on the respective processing node, said controller generating processor control signals enabling, in parallel, each message received by the processor nodes to be stored in the processor slot associated with the processor identified in the message, in the queue slot identified by the count slot associated with the processor identified in the message.
Claim 12
Dependent Claim
53 words
A system as identified in claim 10 in which each processor slot is identified by a memory address, said controller generating processor control signals enabling, the processing node to, in parallel, generate addresses to control storage of messages in each memory in response to their respective message counts in the queue count portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |