Trace cache for a microprocessor-based device

Abstract

Abstract A processor-based device incorporating an on-chip instruction trace cache capable of providing information for reconstructing instruction execution flow. The trace information can be captured without halting normal processor operation. Both serial and parallel communication channels are provided for communicating the trace information to external devices. In the disclosed embodiment of the invention, instructions that disrupt the instruction flow are reported, particularly instructions in which the target address is in some way data dependent. For example, call instructions or unconditional branch instructions in which the target address is provided from a data register (or other memory location such as a stack) cause a trace cache entry to be generated. In the case of many unconditional branches or sequential instructions, no entry is placed into the trace cache because the target address can be completely determined from the instruction stream. Other information provided by the instruction trace cache includes: the target address of a trap or interrupt handler, the target address of a return instruction, addresses from procedure returns, task identifiers, and trace capture stop/start information. The disclosed on-chip instruction trace cache allows less expensive external capture hardware to be utilized and also alleviates various of the bandwidth and clock synchronization issues confronting many existing solutions.

Inventors

• 👤 Daniel Peter Mann

Bibliographic Details