Patent US6141238A successfully refreshed from Google Patents.
US6141238A
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Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same
Assignee: Micron Technology Inc
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Filing: 1999-08-30
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Granted: 2000-10-31
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Expires: 2019-08-30
Abstract
Abstract A memory cell having first and second operating modes includes a transistor comprising a gate adjacent to a channel region coupling source and drain regions, a digitline coupled to one of the source and drain regions, a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor, and a wordline coupled to the gate by the ferroelectric capacitor. Preferably, data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation. A memory cell array, a memory module, and a processor based system can all be fabricated from this memory cell. A method for reading data out of the memory cell in first and second operating modes is also described.
Inventors
- 👤 Leonard Forbes
- 👤 Kie Y. Ahn
- 👤 Wendell P. Noble
- 👤 Alan R. Reinberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/005; G11C11/21; G11C11/22; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B53/00; G11C11/223
Claims Analysis
Total Claims: 71
Claim 1
Independent Claim
61 words
A memory cell comprising: one transistor; and a first capacitor coupled to a gate and a second capacitor coupled to one of a source and a drain region of said transistor, said transistor and said first and second capacitors being arranged to operate in first and second modes of operation which store volatile data and non-volatile data, respectively in said capacitors.
Claim 2
Dependent Claim
61 words
A memory cell comprising: one transistor; and a first capacitor coupled to a gate and a second capacitor coupled to one of a source and a drain region of said transistor, said transistor and said first and second capacitors being arranged to operate in first and second modes of operation which store volatile data and non-volatile data, respectively in said capacitors.
Claim 3
Dependent Claim
20 words
The memory cell as recited in claim 1, wherein the first mode of operation is a dynamic mode of operation.
Claim 4
Dependent Claim
21 words
The memory cell as recited in claim 1, wherein the second mode of operation is a repressed memory mode of operation.
Claim 5
Dependent Claim
20 words
The memory cell as recited in claim 1, wherein one of said first and second capacitors comprises a ferroelectric capacitor.
Claim 6
Dependent Claim
96 words
A memory cell having first and second operating modes, comprising: a transistor comprising a gate adjacent to a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor; and a wordline coupled to the gate by the ferroelectric capacitor, wherein data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation.
Claim 7
Dependent Claim
96 words
A memory cell having first and second operating modes, comprising: a transistor comprising a gate adjacent to a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor; and a wordline coupled to the gate by the ferroelectric capacitor, wherein data is written to and read out of the storage capacitor during the first operating mode and written to and read out of the ferroelectric capacitor during the second mode of operation.
Claim 8
Dependent Claim
20 words
The memory cell as recited in claim 5, wherein the first mode of operation is a dynamic mode of operation.
Claim 9
Dependent Claim
21 words
The memory cell as recited in claim 5, wherein the second mode of operation is a repressed memory mode of operation.
Claim 10
Dependent Claim
45 words
The memory cell as recited in claim 5, wherein: the gate is coupled to the ferroelectric capacitor by polysilicon; the junction formed at the gate has an intrinsic capacitance; and the capacitance of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance.
Claim 11
Dependent Claim
46 words
The memory cell as recited in claim 5, wherein: the gate is coupled to the ferroelectric capacitor by polysilicon; the junction formed at the gate has an intrinsic capacitance; and the physical size of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance.
Claim 12
Dependent Claim
29 words
The memory cell as recited in claim 9, wherein the thickness of a ferroelectric material layer in the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance.
Claim 13
Dependent Claim
76 words
A memory cell storing first and second data types, comprising: a transistor comprising a gate opposing a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions, a ferroelectric capacitor, which stores the second type of data; and a wordline coupled to the gate by the ferroelectric capacitor.
Claim 14
Dependent Claim
76 words
A memory cell storing first and second data types, comprising: a transistor comprising a gate opposing a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions, a ferroelectric capacitor, which stores the second type of data; and a wordline coupled to the gate by the ferroelectric capacitor.
Claim 15
Dependent Claim
17 words
The memory cell as recited in claim 11, wherein the first type of data is transient data.
Claim 16
Dependent Claim
17 words
The memory cell as recited in claim 11, wherein the second type of data is permanent data.
Claim 17
Dependent Claim
45 words
The memory cell as recited in claim 11, wherein: the gate is coupled to the ferroelectric capacitor by polysilicon; the junction formed at the gate has an intrinsic capacitance; and the capacitance of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance.
Claim 18
Dependent Claim
46 words
The memory cell as recited in claim 11, wherein: the gate is coupled to the ferroelectric capacitor by polysilicon; the junction formed at the gate has an intrinsic capacitance; and the physical size of the ferroelectric capacitor is based on the magnitude of the intrinsic capacitance.
Claim 19
Dependent Claim
40 words
The memory cell as recited in claim 11, wherein a first operating voltage required to write the first type of data is less than a second operating voltage required to write the second type of data into the memory cell.
Claim 20
Dependent Claim
17 words
The memory cell as recited in claim 11, wherein the ferroelectric capacitor is an edge-defined ferroelectric capacitor.
Claim 21
Dependent Claim
21 words
The memory cell as recited in claim 11, wherein the ferroelectric capacitor comprises a dielectric layer of lead zirconate titanate (PZT).
Claim 22
Dependent Claim
32 words
The memory cell as recited in claim 18, wherein the PZT comprising the ferroelectric capacitor is of the form PbZr x Ti 1-x O 3 with x ranging between 0.4 and 0.53.
Claim 23
Dependent Claim
85 words
A memory cell array comprising: a plurality of memory cells, each being formed by an arrangement of one transistor and a first capacitor coupled to a gate and a second capacitor coupled to one of a source and a drain region of said transistor, wherein each of the memory cells has first and second modes of operation, the first mode of operation accessing said first capacitor in a first memory plane and the second operating mode accessing said second capacitor in a second memory plane.
Claim 24
Dependent Claim
85 words
A memory cell array comprising: a plurality of memory cells, each being formed by an arrangement of one transistor and a first capacitor coupled to a gate and a second capacitor coupled to one of a source and a drain region of said transistor, wherein each of the memory cells has first and second modes of operation, the first mode of operation accessing said first capacitor in a first memory plane and the second operating mode accessing said second capacitor in a second memory plane.
Claim 25
Dependent Claim
21 words
The memory cell array as recited in claim 20, wherein the first mode of operation is a dynamic mode of operation.
Claim 26
Dependent Claim
22 words
The memory cell array as recited in claim 20, wherein the second mode of operation is a repressed memory mode of operation.
Claim 27
Dependent Claim
33 words
The memory cell array as recited in claim 20, wherein the memory cell array comprises N memory cells, and wherein each of the first and second memory planes stores N bits of data.
Claim 28
Dependent Claim
41 words
The memory cell array as recited in claim 20, wherein the first and second operating modes have respective first and second data writing voltages, and wherein the first data writing voltage is a predetermined percentage of the second data writing voltage.
Claim 29
Dependent Claim
24 words
The memory cell array as recited in claim 24, wherein said first data writing voltage is greater than the threshold voltage of the transistor.
Claim 30
Dependent Claim
122 words
A memory cell array which stores first and second data types in first and second data storage planes, respectively, comprising: a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells comprising: a transistor comprising a gate opposing a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions, a ferroelectric capacitor, which stores the second type of data; and a wordline coupled to the gate by the ferroelectric capacitor; and a sense amplifier coupled to the digitline of the at least one memory cell.
Claim 31
Dependent Claim
122 words
A memory cell array which stores first and second data types in first and second data storage planes, respectively, comprising: a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells comprising: a transistor comprising a gate opposing a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions, a ferroelectric capacitor, which stores the second type of data; and a wordline coupled to the gate by the ferroelectric capacitor; and a sense amplifier coupled to the digitline of the at least one memory cell.
Claim 32
Dependent Claim
18 words
The memory cell array as recited in claim 26, wherein the first data storage plane stores volatile data.
Claim 33
Dependent Claim
18 words
The memory cell array as recited in claim 26, wherein the second data storage plane stores non-volatile data.
Claim 34
Dependent Claim
60 words
The memory cell array as recited in claim 26, wherein data is written into the first data storage plane when the wordline is at a first potential and wherein data is written to the second data storage plane when the wordline is at a second potential higher than the first potential but below the maximum operating voltage of the transistor.
Claim 35
Dependent Claim
48 words
The memory cell array as recited in claim 26, wherein data stored in the first data storage plane corresponds to charge stored in storage capacitor of the memory cell and wherein data stored in the second data storage plane corresponds to the polarization state of the ferroelectric capacitor.
Claim 36
Dependent Claim
50 words
The memory cell array as recited in claim 26, wherein data in the first data storage plane represents the presence or absence of a stored charge and the data in the second data storage plane represents first and second discharge times of the storage capacitor of the respective memory cell.
Claim 37
Dependent Claim
37 words
The memory cell array as recited in claim 31, wherein both the presence or absence of the stored charge and both the first and second discharge times of the storage capacitor are determined by the sense amplifier.
Claim 38
Dependent Claim
52 words
The memory cell array as recited in claim 26, wherein data in the first data storage plane represents the presence or absence of a stored charge and the data in the second data storage plane represents first and second values of the threshold voltage of the transistor of the respective memory cell.
Claim 39
Dependent Claim
43 words
The memory cell array as recited in claim 33, wherein both the presence and absence of the stored charge are determined by the sense amplifier and wherein the first and second values are calculable based on numerical data generated by the sense amplifier.
Claim 40
Dependent Claim
140 words
A processor based system, comprising: a processor; and a memory cell array coupled to the processor, the memory cell array storing first and second data types in first and second data storage planes, respectively, the memory cell array including a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells comprising: a transistor comprising a gate opposing a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions, a ferroelectric capacitor, which stores the second type of data; a wordline coupled to the gate by the ferroelectric capacitor; and a sense amplifier coupled to the digitline of the at least one memory cell.
Claim 41
Dependent Claim
140 words
A processor based system, comprising: a processor; and a memory cell array coupled to the processor, the memory cell array storing first and second data types in first and second data storage planes, respectively, the memory cell array including a plurality of memory cells organized as an array of rows and columns, at least one of the memory cells comprising: a transistor comprising a gate opposing a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor, which stores the first type of data, coupled to the other of the source and drain regions, a ferroelectric capacitor, which stores the second type of data; a wordline coupled to the gate by the ferroelectric capacitor; and a sense amplifier coupled to the digitline of the at least one memory cell.
Claim 42
Dependent Claim
23 words
The processor based system as recited in claim 35, wherein the first data storage plane of the memory cell array stores volatile data.
Claim 43
Dependent Claim
23 words
The processor based system as recited in claim 35, wherein the second data storage plane of the memory cell array stores non-volatile data.
Claim 44
Dependent Claim
65 words
The processor based system as recited in claim 35, wherein, under the control of the processor: data is written into the first data storage plane when the wordline is at a first potential; and data is written to the second data storage plane when the wordline is at a second potential higher that the first potential but below the maximum operating voltage of the transistor.
Claim 45
Dependent Claim
52 words
The processor based system as recited in claim 35, wherein data in the first data storage plane represents the presence or absence of a stored charge and the data in the second data storage plane represents first and second values of the threshold voltage of the transistor of the respective memory cell.
Claim 46
Dependent Claim
46 words
The processor based system as recited in claim 39, wherein both the presence and absence of the stored charge are determined by the sense amplifier and wherein the first and second values are calculated by the processor based on raw data generated by the sense amplifier.
Claim 47
Dependent Claim
146 words
A memory module, comprising: a substrate comprising a circuit board; a plurality of memory chips mounted on the substrate, wherein one or more of the memory chips comprise a memory cell array fabricated on the semiconductor chip communicating with a processor, said memory cell array comprising: a plurality of one transistor/two capacitor (1T/2C) memory cells, wherein the 1T/2C memory cell comprises: a transistor comprising a gate adjacent to a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor; and a wordline coupled to the gate by the ferroelectric capacitor, wherein each of the 1T/2C memory cells has first and second modes of operation, the first mode of operation accessing said first capacitor and the second operating mode accessing said second capacitor.
Claim 48
Dependent Claim
146 words
A memory module, comprising: a substrate comprising a circuit board; a plurality of memory chips mounted on the substrate, wherein one or more of the memory chips comprise a memory cell array fabricated on the semiconductor chip communicating with a processor, said memory cell array comprising: a plurality of one transistor/two capacitor (1T/2C) memory cells, wherein the 1T/2C memory cell comprises: a transistor comprising a gate adjacent to a channel region coupling source and drain regions; a digitline coupled to one of the source and drain regions; a storage capacitor coupled to the other of the source and drain regions, a ferroelectric capacitor; and a wordline coupled to the gate by the ferroelectric capacitor, wherein each of the 1T/2C memory cells has first and second modes of operation, the first mode of operation accessing said first capacitor and the second operating mode accessing said second capacitor.
Claim 49
Dependent Claim
20 words
The memory module as recited in claim 41, wherein the first mode of operation is a dynamic mode of operation.
Claim 50
Dependent Claim
21 words
The memory module as recited in claim 41, wherein the second mode of operation is a repressed memory mode of operation.
Claim 51
Dependent Claim
31 words
The memory module as recited in claim 41, wherein the memory cell array comprises N memory cells, and wherein each of the first and second memory planes stores N bits data.
Claim 52
Dependent Claim
38 words
The memory module as recited in claim 41, wherein the first and second operating modes have respective first and second data writing voltages, and wherein the first operating voltage is a predetermined percentage of the second operating voltage.
Claim 53
Dependent Claim
22 words
The memory module as recited in claim 45, wherein said first operating voltage is greater than the threshold voltage of the transistor.
Claim 54
Independent Claim
81 words
A method for reading information from a one transistor/two capacitor (1T/2C) memory cell in which a first capacitor is coupled to a gate and a second capacitor is coupled to one of a source and a drain region of said transistor, the method comprising: reading a first data value from a first of the two capacitors in a first mode of operation; and reading a second data value from a second of the two capacitors in a second mode of operation.
Claim 55
Independent Claim
81 words
A method for reading information from a one transistor/two capacitor (1T/2C) memory cell in which a first capacitor is coupled to a gate and a second capacitor is coupled to one of a source and a drain region of said transistor, the method comprising: reading a first data value from a first of the two capacitors in a first mode of operation; and reading a second data value from a second of the two capacitors in a second mode of operation.
Claim 56
Dependent Claim
19 words
The method as recited in claim 47, wherein the first mode of operation is a dynamic mode of operation.
Claim 57
Dependent Claim
20 words
The method as recited in claim 47, wherein the second mode of operation is a repressed memory mode of operation.
Claim 58
Dependent Claim
17 words
The method as recited in claim 47, wherein one of the two capacitors comprises a ferroelectric capacitor.
Claim 59
Dependent Claim
66 words
The method as recited in claim 47, wherein the transistor further comprises a control gate, and wherein the step of reading the first data value from the first capacitor in the first mode of operation comprises: applying a voltage a voltage in excess of a threshold voltage of the transistor to the control gate; and sensing a potential of a charge stored in the first capacitor.
Claim 60
Dependent Claim
58 words
The method as recited in claim 47, wherein the transistor further comprises a control gate, and wherein the step of reading the second data value derived from a state of the second capacitor comprises: applying a voltage approximately equal to the threshold voltage of the transistor to the control gate; and sensing a response time of the transistor.
Claim 61
Independent Claim
81 words
A method for writing information to a one transistor/two capacitor (1T/2C) memory cell in which a first capacitor is coupled to a gate and a second capacitor is coupled to one of a source and a drain region of said transistor, the method comprising: writing a first data value to a first of the two capacitors in a first mode of operation; and writing a second data value to a second of the two capacitors in a second mode of operation.
Claim 62
Independent Claim
81 words
A method for writing information to a one transistor/two capacitor (1T/2C) memory cell in which a first capacitor is coupled to a gate and a second capacitor is coupled to one of a source and a drain region of said transistor, the method comprising: writing a first data value to a first of the two capacitors in a first mode of operation; and writing a second data value to a second of the two capacitors in a second mode of operation.
Claim 63
Dependent Claim
19 words
The method as recited in claim 52, wherein the first mode of operation is a dynamic mode of operation.
Claim 64
Dependent Claim
20 words
The method as recited in claim 54, wherein the second mode of operation is a repressed memory mode of operation.
Claim 65
Dependent Claim
17 words
The method as recited in claim 52, wherein one of the two capacitors comprises a ferroelectric capacitor.
Claim 66
Dependent Claim
53 words
The method as recited in claim 52, wherein the second of the two capacitors comprises a ferroelectric capacitor and wherein the step of writing the second data value further comprises applying a potential greater than the coercive voltage of the ferroelectric capacitor to thereby write the second data value to the ferroelectric capacitor.
Claim 67
Dependent Claim
26 words
The method as recited in claim 52, wherein a predetermined digital value is written into the ferroelectric capacitor when the applied potential has a predetermined polarity.
Claim 68
Independent Claim
78 words
A method for forming a memory cell, said method comprising: forming source and drain regions in a substrate well; forming a gate between said source and drain regions; forming a first ferroelectric capacitor on said gate with a first conductor of said ferroelectric capacitor coupled to said gate; forming a wordline conductor on a second conductor of said ferroelectric capacitor; and forming a second capacitor having one conductor electrically coupled to one of said source and drain regions.
Claim 69
Independent Claim
78 words
A method for forming a memory cell, said method comprising: forming source and drain regions in a substrate well; forming a gate between said source and drain regions; forming a first ferroelectric capacitor on said gate with a first conductor of said ferroelectric capacitor coupled to said gate; forming a wordline conductor on a second conductor of said ferroelectric capacitor; and forming a second capacitor having one conductor electrically coupled to one of said source and drain regions.
Claim 70
Dependent Claim
43 words
A method as in claim 59 wherein said ferroelectric capacitor is formed by a first layer of Pt, a layer of ferroelectric material over said first layer of Pt material, and a second layer of Pt material over said layer of ferroelectric material.
Claim 71
Dependent Claim
34 words
A method as in claim 60 wherein said first layer of Pt is provided on a layer of polysilicon forming said gate and said wordline conductor is connected to said second layer of Pt.
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