US6110772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit and manufacturing method thereof
Assignee: Semiconductor Components Industries LLC
•
Filing: 1998-01-30
•
Granted: 2000-08-29
•
Expires: 2018-01-30
Abstract
Abstract A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer. The lower and upper electrodes of the capacitor may be formed using an a-Si layer, similar to the resistance layer.
Inventors
- 👤 Tadayoshi Takada
- 👤 Tsuyoshi Takahashi
- 👤 Yasunari Tagami
- 👤 Hirotsugu Hata
- 👤 Satoru Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:26
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D1/00; H10D1/40; H10D1/47; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
149 words
A method for manufacturing a semiconductor device carrying a capacitor and a resistance element being integrated on a single circuit substrate, comprising steps of: forming a first insulating layer on either the substrate of the semiconductor device or a predetermined semiconductor layer; forming an a-Si layer on a surface of the first insulating layer; doping the a-Si layer with impurities; heating the a-Si layer doped with impurities to diffuse the impurities to thereby form a first lower electrode; forming a second insulating layer on the first lower electrode, having an opening where the first lower electrode is partially exposed; forming a SiN dielectric layer in the opening and on a predetermined resistance layer formation region; and forming an a-Si layer covering the opening and the resistance layer formation region on the surface of the SiN dielectric layer to therewith constitute a first upper electrode and a resistance layer, respectively.
Claim 2
Independent Claim
149 words
A method for manufacturing a semiconductor device carrying a capacitor and a resistance element being integrated on a single circuit substrate, comprising steps of: forming a first insulating layer on either the substrate of the semiconductor device or a predetermined semiconductor layer; forming an a-Si layer on a surface of the first insulating layer; doping the a-Si layer with impurities; heating the a-Si layer doped with impurities to diffuse the impurities to thereby form a first lower electrode; forming a second insulating layer on the first lower electrode, having an opening where the first lower electrode is partially exposed; forming a SiN dielectric layer in the opening and on a predetermined resistance layer formation region; and forming an a-Si layer covering the opening and the resistance layer formation region on the surface of the SiN dielectric layer to therewith constitute a first upper electrode and a resistance layer, respectively.
Claim 3
Dependent Claim
116 words
A method for manufacturing a semiconductor device according to claim 1, further comprising steps of: forming a third insulating layer covering substantially an entire surface of the substrate after the a-Si layer is formed; forming a number of openings at predetermined portions of the third insulating layer; forming a second lower electrode contacting the first lower electrode of the capacitor at one of the number of openings; forming a second upper electrode contacting the first upper electrode of the capacitor at another one of the number of openings; and forming a first resistance electrode and a second resistance electrode contacting the resistance layer of the resistance element at still another one of the number of openings.
Claim 4
Dependent Claim
39 words
A method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a SiN layer for being used as a base of the lower electrode before the lower electrode of the capacitor is formed.
Claim 5
Dependent Claim
24 words
A method for manufacturing a semiconductor device according to claim 1, wherein the a-Si layer is formed at approximately 520° C. to 580° C.
Claim 6
Independent Claim
147 words
A method for manufacturing a semiconductor device carrying a capacitor and a resistance element being integrated on a single circuit substrate, comprising steps of: doping with impurities either the substrate of the semiconductor device or a semiconductor layer at a predetermined region; diffusing impurities in either the substrate of the semiconductor device or the semiconductor layer to form an impurity diffused region; forming a first lower electrode using the impurity diffused region; forming a first insulating layer on the first lower electrode having an opening where the first lower electrode is partially exposed; forming a SiN dielectric layer covering the opening and a predetermined resistance layer formation region on the second insulating layer; and forming an a-Si layer covering the opening and the resistance layer formation region on the surface of the SiN dielectric layer to therewith constitute a first upper electrode and a resistance layer, respectively.
Claim 7
Independent Claim
147 words
A method for manufacturing a semiconductor device carrying a capacitor and a resistance element being integrated on a single circuit substrate, comprising steps of: doping with impurities either the substrate of the semiconductor device or a semiconductor layer at a predetermined region; diffusing impurities in either the substrate of the semiconductor device or the semiconductor layer to form an impurity diffused region; forming a first lower electrode using the impurity diffused region; forming a first insulating layer on the first lower electrode having an opening where the first lower electrode is partially exposed; forming a SiN dielectric layer covering the opening and a predetermined resistance layer formation region on the second insulating layer; and forming an a-Si layer covering the opening and the resistance layer formation region on the surface of the SiN dielectric layer to therewith constitute a first upper electrode and a resistance layer, respectively.
Claim 8
Dependent Claim
117 words
A method for manufacturing a semiconductor device according to claim 5, further comprising steps of: forming a second insulating layer covering substantially an entire upper surface of the substrate after the a-Si layer is formed; forming a number of openings at predetermined portions of the second insulating layer; forming a second lower electrode contacting the first lower electrode of the capacitor at one of the number of openings; forming a second upper electrode contacting the first upper electrode of the capacitor at another one of the number of openings; and forming a first resistance electrode and a second resistance electrode contacting the resistance layer of the resistance element at still another one of the number of openings.
Claim 9
Dependent Claim
24 words
A method for manufacturing a semiconductor device according to claim 5, wherein the a-Si layer is formed at approximately 520° C. to 580° C.
References Cited (Backward Citations)
JPS62163358A
Cited
US4812417A
Cited
US4753709A
Cited
US4762801A
Cited
US5109262A
Cited
US5324983A
Cited
US5350948A
Cited
US5622887A
Cited
US5479047A
Cited
US5420053A
Cited
JPH07235547A
Cited
US5504018A
Cited
US5955775A
Cited
US5904508A
Cited
US5759887A
Cited
US5714415A
Cited
US5798561A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-29 | 2004-02-28 | 2004-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-29 | 2008-02-28 | 2008-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-29 | 2012-02-28 | 2012-08-29 | $7700.00 | Window Closed / Lapsed |