US5420053A
Expired / Lapsed
US
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Method for manufacturing semiconductor device having bipolar transistor and polycrystalline silicon resistor
Assignee: Renesas Electronics Corp
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Filing: 1994-05-04
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Granted: 1995-05-30
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Expires: 2014-05-04
Abstract
Abstract A collector region is formed in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate, and a non-monocrystalline silicon layer is deposited thereon. The non-monocrystalline silicon layer is annealed to obtain a polycrystalline silicon layer which is patterned into a polycrystalline silicon resistor. The polycrystalline silicon resistor is covered by an insulating layer. Thereafter, a base region is formed, and an emitter region is formed in the base region.
Inventors
- 👤 Shinichi Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:38
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011; Y10S148/136
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
170 words
A method for manufacturing a semiconductor device comprising the steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a first silicon nitride layer on said first silicon oxide layer; forming a non-monocrystalline silicon layer including impurities on said first silicon nitride layer; annealing said non-monocrystalline silicon layer convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; forming a second silicon oxide layer on said patterned polycrystalline silicon layer; etching said second silicon oxide layer using said first silicon nitride layer as an etching stopper, so that said second silicon oxide layer covers only said patterned polycrystalline silicon layer: etching said first silicon nitride layer using said second silicon oxide layer as a mask and said first silicon oxide layer as an etching stopper; ion-implanting impurities into said collector region through said first silicon oxide layer so that a base region is formed within said collector region; and forming an emitter region within said base region.
Claim 2
Independent Claim
170 words
A method for manufacturing a semiconductor device comprising the steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a first silicon nitride layer on said first silicon oxide layer; forming a non-monocrystalline silicon layer including impurities on said first silicon nitride layer; annealing said non-monocrystalline silicon layer convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; forming a second silicon oxide layer on said patterned polycrystalline silicon layer; etching said second silicon oxide layer using said first silicon nitride layer as an etching stopper, so that said second silicon oxide layer covers only said patterned polycrystalline silicon layer: etching said first silicon nitride layer using said second silicon oxide layer as a mask and said first silicon oxide layer as an etching stopper; ion-implanting impurities into said collector region through said first silicon oxide layer so that a base region is formed within said collector region; and forming an emitter region within said base region.
Claim 3
Dependent Claim
18 words
A method as set forth in claim 1, wherein said non-monocrystalline silicon layer is made of polycrystalline silicon.
Claim 4
Dependent Claim
34 words
A method as set forth in claim 2, wherein said annealling step comprises a step of carrying out an annealling operation at a temperature of about 800° to 1000° C. for about one hour.
Claim 5
Dependent Claim
18 words
A method as set forth in claim 1, wherein said non-monocrystalline silicon layer is made of amorphous silicon.
Claim 6
Dependent Claim
34 words
A method as set forth in claim 4, wherein said annealling step comprises a step of carrying out an annealling operation at a temperature of about 500° to 600° C. for about ten hours.
Claim 7
Dependent Claim
29 words
A method as set forth in claim 1, wherein said base region forming step comprises a step of implanting doping impurities into said collector region by a heating process.
Claim 8
Dependent Claim
27 words
A method as set forth in claim 1, further comprising a step of forming a second silicon nitride layer at least on said second silicon oxide layer.
Claim 9
Dependent Claim
31 words
A method as set forth in claim 7, wherein said second silicon nitride layer forming step includes a step of forming said second silicon nitride layer by a low-pressure CVD process.
Claim 10
Independent Claim
172 words
A method for manufacturing a semiconductor device comprising steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a first silicon nitride layer on said first silicon oxide layer; forming a non-monocrystalline silicon layer including impurities on said first silicon nitride layer; annealing said non-monocrystalline silicon layer to convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; forming a second silicon oxide layer on said patterned polycrystalline silicon layer; etching said second silicon oxide layer using said first silicon nitride layer as an etching stopper, so that said second silicon oxide layer covers only said patterned polycrystalline silicon layer: etching said first silicon nitride layer using said second silicon oxide layer as a mask and said first silicon oxide layer as an etching stopper; Implanting impurities into said collector region through said first silicon oxide layer so that a base region is formed within said collector region by diffusion; and forming an emitter region within said base region.
Claim 11
Independent Claim
172 words
A method for manufacturing a semiconductor device comprising steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a first silicon nitride layer on said first silicon oxide layer; forming a non-monocrystalline silicon layer including impurities on said first silicon nitride layer; annealing said non-monocrystalline silicon layer to convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; forming a second silicon oxide layer on said patterned polycrystalline silicon layer; etching said second silicon oxide layer using said first silicon nitride layer as an etching stopper, so that said second silicon oxide layer covers only said patterned polycrystalline silicon layer: etching said first silicon nitride layer using said second silicon oxide layer as a mask and said first silicon oxide layer as an etching stopper; Implanting impurities into said collector region through said first silicon oxide layer so that a base region is formed within said collector region by diffusion; and forming an emitter region within said base region.
Claim 12
Dependent Claim
18 words
A method as set forth in claim 9, wherein said non-monocrystalline silicon layer is made of polycrystalline silicon.
Claim 13
Dependent Claim
34 words
A method as set forth in claim 10, wherein said annealling step comprises a step of carrying out an annealling operation at a temperature of about 800° to 1000° C. for about one hour.
Claim 14
Dependent Claim
18 words
A method as set forth in claim 9, wherein said non-monocrystalline silicon layer is made of amorphous silicon.
Claim 15
Dependent Claim
33 words
A method as set forth in claim 12, wherein said annealling step comprises a step of carrying out an annealling operation at a temperature of about 500to 600° C. for about ten hours.
Claim 16
Dependent Claim
27 words
A method as set forth in claim 9, further comprising a step of forming a second silicon nitride layer at least on said second silicon oxide layer.
Claim 17
Dependent Claim
32 words
A method as set forth in claim 14, wherein said second silicon nitride layer forming step includes a step of forming said second silicon nitride layer by a low pressure CVD process.
Claim 18
Independent Claim
122 words
A method for manufacturing a semiconductor device comprising the steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a non-monocrystalline silicon layer including impurities on said first silicon oxide layer; annealling said non-monocrystalline silicon layer to convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; covering said patterned polycrystalline silicon layer with a second silicon oxide layer; forming an opening in said first silicon oxide layer after said covering step is carried out, said opening reaching said collector region; growing an epitaxial layer having impurities in said opening so that said epitaxial layer serves as a base region; and forming an emitter region within said base region.
Claim 19
Independent Claim
122 words
A method for manufacturing a semiconductor device comprising the steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a non-monocrystalline silicon layer including impurities on said first silicon oxide layer; annealling said non-monocrystalline silicon layer to convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; covering said patterned polycrystalline silicon layer with a second silicon oxide layer; forming an opening in said first silicon oxide layer after said covering step is carried out, said opening reaching said collector region; growing an epitaxial layer having impurities in said opening so that said epitaxial layer serves as a base region; and forming an emitter region within said base region.
Claim 20
Dependent Claim
18 words
A method as set forth in claim 16, wherein said non-monocrystalline silicon layer is made of polycrystalline silicon.
Claim 21
Dependent Claim
34 words
A method as set forth in claim 17, wherein said annealling step comprises a step of carrying out an annealling operation at a temperature of about 800° to 1000° C. for about one hour.
Claim 22
Dependent Claim
18 words
A method as set forth in claim 16, wherein said non-monocrystalline silicon layer is made of amorphous silicon.
Claim 23
Dependent Claim
34 words
A method as set forth in claim 19, wherein said annealling step comprises a step of carrying out an annealling operation at a temperature of about 500° to 600° C. for about ten hours.
Claim 24
Dependent Claim
25 words
A method as set forth in claim 16, further comprising a step of forming a first silicon nitride layer on said first silicon oxide layer.
Claim 25
Dependent Claim
27 words
A method as set forth in claim 16, further comprising a step of forming a second silicon nitride layer at least on said second silicon oxide layer.
Claim 26
Dependent Claim
31 words
A method as set forth in claim 21, wherein said second silicon nitride layer forming step includes a step of forming said second silicon nitride layer by a low-pressure CVD process.
Claim 27
Independent Claim
193 words
A method for manufacturing a semiconductor device comprising the steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a first silicon nitride layer on said first silicon oxide layer; forming a non-monocrystalline silicon layer including impurities on said first silicon nitride layer; annealing said non-monocrystalline silicon layer to convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; forming a second silicon oxide layer on said patterned polycrystalline silicon layer; etching said second silicon oxide layer using said first silicon nitride layer as an etching stopper, so that said second silicon oxide layer covers only said patterned polycrystalline silicon .layer; etching said first silicon nitride layer using said second silicon oxide layer as a mask and said first silicon oxide layer as an etching stopper; forming an opening in said first silicon oxide layer, after said first silicon nitride layer etching step is carried out, said opening reaching said collector region; growing an epitaxial layer having impurities in said opening so that said epitaxial layer serves as a base region; and forming an emitter region within said base region.
Claim 28
Independent Claim
193 words
A method for manufacturing a semiconductor device comprising the steps of: forming a collector region in a semiconductor substrate; forming a first silicon oxide layer on said semiconductor substrate; forming a first silicon nitride layer on said first silicon oxide layer; forming a non-monocrystalline silicon layer including impurities on said first silicon nitride layer; annealing said non-monocrystalline silicon layer to convert it into a polycrystalline silicon layer; patterning said polycrystalline silicon layer; forming a second silicon oxide layer on said patterned polycrystalline silicon layer; etching said second silicon oxide layer using said first silicon nitride layer as an etching stopper, so that said second silicon oxide layer covers only said patterned polycrystalline silicon .layer; etching said first silicon nitride layer using said second silicon oxide layer as a mask and said first silicon oxide layer as an etching stopper; forming an opening in said first silicon oxide layer, after said first silicon nitride layer etching step is carried out, said opening reaching said collector region; growing an epitaxial layer having impurities in said opening so that said epitaxial layer serves as a base region; and forming an emitter region within said base region.
Claim 29
Dependent Claim
18 words
A method as set forth in claim 23, wherein said non-monocrystalline silicon layer is made of polycrystalline silicon.
Claim 30
Dependent Claim
34 words
A method as set forth in claim 24, wherein said annealling step comprises a step of carrying out an annealing operation at a temperature of about 800° to 1000° C. for about one hour.
Claim 31
Dependent Claim
18 words
A method as set forth in claim 23, wherein said non-monocrystalline silicon layer is made of amorphous silicon.
Claim 32
Dependent Claim
34 words
A method as set forth in, claim 26, wherein said annealling step comprises a step of carrying out an annealing operation at a temperature of about 500° to 600° C. for about ten hours.
Claim 33
Dependent Claim
27 words
A method as set forth in claim 23, further comprising a step of forming a second silicon nitride layer at least on said second silicon oxide layer.
Claim 34
Dependent Claim
31 words
A method as set forth in claim 28, wherein said second silicon nitride layer forming step includes a step of forming said second silicon nitride layer by a low-pressure CVD process.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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