Patent US6105141A successfully refreshed from Google Patents.
US6105141A
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US
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Method and apparatus for power management of an external cache of a computer system
Assignee: Apple Inc
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Filing: 1998-06-04
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Granted: 2000-08-15
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Expires: 2018-06-04
Abstract
Abstract Power management techniques for external cache memories of computers are disclosed. The power management techniques operate to reduce power consumption of an external cache memory of a computer system by intelligently placing the external cache memory in a low power mode. In one embodiment of the invention, a computer operates using event loop and an idle loop. The computer generally remains in the event loop while there is activity that requires processing, but enters the idle loop when there is no activity so that power consumption is lowered. The power management techniques according to the invention reduce power consumption of the computer by placing the external cache memory in the low power state upon entering the idle loop, and then awakening the external cache memory as the microprocessor awakens or upon exiting the idle loop. The power savings provided by the invention are particularly suitable for use with battery powered computing devices.
Inventors
- 👤 Michael S. Hanlon
- 👤 Michael E. Larson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:05
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3206; G06F1/3215; G06F1/3225; G06F1/3234; G06F1/325; G06F1/3275; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
149 words
A method for reducing power consumption of a computer system, the computer system including a processor, system memory, and an external cache memory, said method comprising: (a) entering an idle mode in which the processor and the external cache memory are in a sleep state; (b) determining whether an interrupt has occurred; (c) awakening the processor from the sleep state to a normal state and not awakening the external cache memory when said determining (b) determines that an interrupt has occurred; (d) servicing the interrupt; (e) performing idle processing without use of the external cache memory which remains in the sleep state; (f) determining whether the idle mode should be exited and a normal mode entered; and (g) awakening the external cache memory from the sleep state to a normal state when said determining (f) determines that the idle mode is to be exited and the normal mode entered.
Claim 2
Independent Claim
149 words
A method for reducing power consumption of a computer system, the computer system including a processor, system memory, and an external cache memory, said method comprising: (a) entering an idle mode in which the processor and the external cache memory are in a sleep state; (b) determining whether an interrupt has occurred; (c) awakening the processor from the sleep state to a normal state and not awakening the external cache memory when said determining (b) determines that an interrupt has occurred; (d) servicing the interrupt; (e) performing idle processing without use of the external cache memory which remains in the sleep state; (f) determining whether the idle mode should be exited and a normal mode entered; and (g) awakening the external cache memory from the sleep state to a normal state when said determining (f) determines that the idle mode is to be exited and the normal mode entered.
Claim 3
Dependent Claim
44 words
A method as recited in claim 1, wherein said entering (a) the idle mode comprises: (a1) preparing the external cache memory for the sleep state; (a2) placing the external cache memory in the sleep state; and (a3) placing the microprocessor in the sleep state.
Claim 4
Dependent Claim
24 words
A method as recited in claim 2, wherein said preparing (a1) includes flushing out content of the external cache memory to the system memory.
Claim 5
Dependent Claim
25 words
A method as recited in claim 3, wherein said method further comprises: (h) initializing the content of the external cache memory following said awakening (g).
Claim 6
Dependent Claim
18 words
A method as recited in claim 1, wherein during the idle processing the processor performs background processing tasks.
Claim 7
Dependent Claim
24 words
A method as recited in claim 1, wherein said entering (a) of the idle mode occurs when the normal mode lacks events to process.
Claim 8
Dependent Claim
44 words
A method as recited in claim 1, wherein said entering (a) the idle mode comprises: (a1) flushing the external cache memory for the sleep state; (a2) placing the external cache memory in the sleep state; and (a3) placing the microprocessor in the sleep state.
Claim 9
Dependent Claim
31 words
A method as recited in claim 7, wherein said awakening (g) of the external cache memory places the external cache memory in the normal state and initializes the external cache memory.
Claim 10
Dependent Claim
16 words
A method as recited in claim 7, wherein said computer system is a portable computer system.
Claim 11
Dependent Claim
40 words
A method as recited in claim 1, wherein the sleep state is a low powered state in which the microprocessor either does not execute instructions or does execute instructions at a substantially slowed speed as compared to the normal state.
Claim 12
Dependent Claim
26 words
A method as recited in claim 1, wherein said determining of whether the idle mode should be exited is done based on the presence of activity.
Claim 13
Dependent Claim
43 words
A method as recited in claim 1, wherein the computer system further includes an internal cache memory integral with the processor, the integral cache memory in set in either a sleep state or a normal state based on the state of the processor.
Claim 14
Dependent Claim
41 words
A method as recited in claim 1, wherein said method further comprises: (h) returning the processor to the sleep state after the interrupt has been serviced and when said determining (f) determines that the idle mode is not to be exited.
Claim 15
Dependent Claim
186 words
A computer system, comprising: a microprocessor for executing instructions associated with an event loop or an idle loop, said microprocessor including an internal primary cache memory for temporarily storing data for use by said microprocessor, said microprocessor having a normal power mode and a low power mode; an external secondary cache memory for temporarily storing data for use by said microprocessor, said microprocessor having a normal power mode and a low power mode; and a power management unit operatively connected to said microprocessor and said external cache memory, said power management unit controls whether said microprocessor and said external secondary cache memory are placed in either the normal power mode or the low power mode, respectively, wherein in the event loop, said microprocessor and said external secondary cache memory are in the normal power mode, and wherein in the idle loop, said microprocessor is mostly in the low power mode but periodically said microprocessor is in the normal power mode to service an interrupt and perform idle processing, and said external secondary cache memory always remains in the low power mode while in the idle loop.
Claim 16
Dependent Claim
186 words
A computer system, comprising: a microprocessor for executing instructions associated with an event loop or an idle loop, said microprocessor including an internal primary cache memory for temporarily storing data for use by said microprocessor, said microprocessor having a normal power mode and a low power mode; an external secondary cache memory for temporarily storing data for use by said microprocessor, said microprocessor having a normal power mode and a low power mode; and a power management unit operatively connected to said microprocessor and said external cache memory, said power management unit controls whether said microprocessor and said external secondary cache memory are placed in either the normal power mode or the low power mode, respectively, wherein in the event loop, said microprocessor and said external secondary cache memory are in the normal power mode, and wherein in the idle loop, said microprocessor is mostly in the low power mode but periodically said microprocessor is in the normal power mode to service an interrupt and perform idle processing, and said external secondary cache memory always remains in the low power mode while in the idle loop.
Claim 17
Dependent Claim
25 words
A method as recited in claim 14, wherein the low power mode is an inactive state, and the normal power mode is an active state.
Claim 18
Dependent Claim
17 words
A computer system as recited in claim 14, wherein said computer system is a portable computer system.
Claim 19
Dependent Claim
18 words
A computer system as recited in claim 14, wherein said computer system is a hand-held portable computer system.
Claim 20
Dependent Claim
195 words
A computer readable medium including at least computer program code for reducing power consumption of a computer system, the computer system including a processor, system memory, and an external cache memory, said computer readable medium comprising: computer program code for entering an idle mode and having the processor and the external cache memory in a sleep state; computer program code for determining whether an interrupt has occurred; computer program code for awakening the processor from the sleep state to a normal state and not awakening the external cache memory when said computer program code for determining determines that an interrupt has occurred; computer program code for servicing the interrupt; computer program code for performing idle processing with use of the processor in the normal state and without use of the external cache memory which remains in the sleep state; computer program code for determining whether the idle mode should be exited and a normal mode entered; and computer program code for awakening the external cache memory from the sleep state to a normal state when said computer program code for determining determines that the idle mode is to be exited and the normal mode entered.
Claim 21
Dependent Claim
195 words
A computer readable medium including at least computer program code for reducing power consumption of a computer system, the computer system including a processor, system memory, and an external cache memory, said computer readable medium comprising: computer program code for entering an idle mode and having the processor and the external cache memory in a sleep state; computer program code for determining whether an interrupt has occurred; computer program code for awakening the processor from the sleep state to a normal state and not awakening the external cache memory when said computer program code for determining determines that an interrupt has occurred; computer program code for servicing the interrupt; computer program code for performing idle processing with use of the processor in the normal state and without use of the external cache memory which remains in the sleep state; computer program code for determining whether the idle mode should be exited and a normal mode entered; and computer program code for awakening the external cache memory from the sleep state to a normal state when said computer program code for determining determines that the idle mode is to be exited and the normal mode entered.
Claim 22
Dependent Claim
49 words
A computer readable medium as recited in claim 18, wherein said method further comprises: computer program code for returning the processor to the sleep state after the interrupt has been serviced and when said computer program code for determining determines that the idle mode is not to be exited.
Claim 23
Dependent Claim
58 words
A computer readable medium as recited in claim 18, wherein said computer program code for entering the idle mode comprises: computer program code for preparing the external cache memory for the sleep state; computer program code for placing the external cache memory in the sleep state; and computer program code for placing the microprocessor in the sleep state.
Claim 24
Dependent Claim
33 words
A computer readable medium as recited in claim 20, wherein said method further comprises: computer program code for initializing the content of the external cache memory following said computer program code for awakening.
Claim 25
Dependent Claim
42 words
A computer readable medium as recited in claim 18, wherein during the idle processing the processor performs background processing tasks, and wherein said computer program code for entering of the idle mode is performed when the normal mode lacks events to process.
Claim 26
Dependent Claim
36 words
A computer readable medium as recited in claim 18, wherein said computer program code for awakening of the external cache memory places the external cache memory in the normal state and initializes the external cache memory.
Claim 27
Dependent Claim
18 words
A computer readable medium as recited in claim 18, wherein said computer system is a portable computer system.
Claim 28
Dependent Claim
42 words
A computer readable medium as recited in claim 18, wherein the sleep state is a low powered state in which the microprocessor either does not execute instructions or does execute instructions at a substantially slowed speed as compared to the normal state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-15 | 2004-02-14 | 2004-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-15 | 2008-02-14 | 2008-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-15 | 2012-02-14 | 2012-08-15 | $7700.00 | Window Closed / Lapsed |