Microcomputer development support system operable with only background monitor and without cache replacement

Claim 1

A microcomputer development support system for a microprocessor, said microprocessor including therein an execution unit for executing a program and a cache memory associated with said execution unit, said microprocessor for inhibiting a cache registration in a cache replacement access to said cache memory, and for putting said cache memory into a "cache off" condition in a programmed manner, said microprocessor generating a break acknowledge signal when said execution unit has executed a predetermined branch instruction, the microcomputer development support system comprising: instruction substituting means for tracing a memory access of said microcomputer and for responding to a break request signal to supply said execution unit of said microcomputer with said predetermined branch instruction in place of an instruction which has been read from a predetermined address of a user memory to be supplied to said microcomputer; a background monitor for providing said microprocessor a memory space which is separated from a user space but peculiar to the microcomputer development support system; a breakpoint register for registering an address where a break processing is to be performed; a comparator for comparing a content of said breakpoint register with an address outputted from said microcomputer, and for generating said break request signal when coincidence is detected; a memory space switching circuit for receiving said break acknowledge signal and said address outputted from said microprocessor, for separating said background monitor from said user memory, so that said background monitor functions as the memory space which is separated from the user space but is peculiar to the microcomputer development support system, whereby after said break request signal is activated, a processing is performed based on a program of said background monitor, said microcomputer for responding to said break request signal to put said cache memory into said "cache off" condition when said program of said background monitor begins to execute, said microcomputer returning said cache memory into a "cache on" condition when the execution of said program of said background monitor is terminated, wherein said background monitor generates a cache registration invalid signal when said execution unit of said microcomputer is supplied with said predetermined branch instruction in place of the instruction which has been read from said user memory to be supplied to said microcomputer, wherein said instruction substituting means is located externally of said microprocessor, said development support system further comprising an OR circuit for receiving said break request signal and said cache registration invalid signal and for generating a cache registration control signal, and wherein said microcomputer generates a logical product of said cache registration control signal and a cache write signal outputted from said execution unit to said cache memory, and to inhibit, when said logical product is active, said branch instruction from being registered into said cache memory.