Power and signal routing technique for gate array design

Claim 2

In an integrated circuit implementing a standard cell architecture organized in rows and columns of basic cells, a layout architecture, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of first traces on the first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit predominantly in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces; a plurality of third traces on the third metal layer extending across the integrated circuit predominantly in a direction parallel to the columns; and a plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.

Claim 3

The layout architecture of claim 1, wherein the plurality of second traces include power carrying traces.

Claim 4

The layout architecture of claim 1, wherein the first traces are not used for global power distribution.

Claim 5

The integrated circuit of claim 1 wherein no metal layer is disposed between the first metal layer and the basic cells.

Claim 6

In an integrated circuit implementing a standard cell architecture organized in rows and columns of basic cells, a layout architecture, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of first traces on the first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit predominantly in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces and power carrying traces, wherein the power carrying traces are directly above diffusion regions of the basic cells; a plurality of third traces on the third metal layer extending across the integrated circuit predominantly in a direction parallel to the columns; and a plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.

Claim 7

In an integrated circuit implementing a standard cell architecture organized in rows and columns of basic cells, a layout architecture, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of first traces on the first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit predominantly in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces and power carrying traces, wherein the power carrying traces are directly above diffusion regions of the basic cells; a plurality of third traces on the third metal layer extending across the integrated circuit predominantly in a direction parallel to the columns; and a plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.

Claim 8

In an integrated circuit implementing a standard cell architecture organized in rows and columns of basic cells, a layout architecture, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of first traces on the first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit predominantly in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces and power carrying traces, wherein the power carrying traces are directly above substrate contacts; a plurality of third traces on the third metal layer extending across the integrated circuit predominantly in a direction parallel to the columns; and a plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.

Claim 9

In an integrated circuit implementing a standard cell architecture organized in rows and columns of basic cells, a layout architecture, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of first traces on the first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit predominantly in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces and power carrying traces, wherein the power carrying traces are directly above substrate contacts; a plurality of third traces on the third metal layer extending across the integrated circuit predominantly in a direction parallel to the columns; and a plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.

Claim 10

An integrated circuit architecture for a gate array, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of basic cells arranged as an array in rows and columns, each basic cell comprising: a diffusion region; and a gate region extending across the diffusion region in a vertical direction; a plurality of first conductive traces on a first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, the first conductive traces including global interconnection signal carrying traces; a plurality of second conductive traces on the second metal layer, the second conductive traces extending across the integrated circuit predominantly in a directions parallel to the rows; and a plurality of third conductive traces on the third metal layer, the third conductive traces extending across the integrated circuit predominantly in a direction parallel to the columns.

Claim 11

An integrated circuit architecture for a gate array, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of basic cells arranged as an array in rows and columns, each basic cell comprising: a diffusion region; and a gate region extending across the diffusion region in a vertical direction; a plurality of first conductive traces on a first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, the first conductive traces including global interconnection signal carrying traces; a plurality of second conductive traces on the second metal layer, the second conductive traces extending across the integrated circuit predominantly in a directions parallel to the rows; and a plurality of third conductive traces on the third metal layer, the third conductive traces extending across the integrated circuit predominantly in a direction parallel to the columns.

Claim 12

The integrated circuit architecture of claim 7, wherein the first conductive traces include local interconnections for the basic cells.

Claim 13

The integrated circuit architecture of claim 7, wherein the second conductive traces include power carrying traces that are coupled to a power supply source.

Claim 14

The integrated circuit architecture of claim 6 wherein the second conductive traces include global interconnect traces extending across the integrated circuit predominantly in the direction parallel to the rows.

Claim 15

An integrated circuit architecture for a gate array, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of basic cells arranged as an array in rows and columns, each basic cell comprising: a diffusion region; and a gate region extending across the diffusion region in a vertical direction; a plurality of first conductive traces on a first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, the first conductive traces including global interconnection signal carrying traces; a plurality of second conductive traces on the second metal layer, the second conductive traces being directly above the diffusion region and coupled to a power supply source and extending across the integrated circuit predominantly in a directions parallel to the rows; and a plurality of third conductive traces on the third metal layer, the third conductive traces extending across the integrated circuit predominantly in a direction parallel to the columns.

Claim 16

An integrated circuit architecture for a gate array, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of basic cells arranged as an array in rows and columns, each basic cell comprising: a diffusion region; and a gate region extending across the diffusion region in a vertical direction; a plurality of first conductive traces on a first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, the first conductive traces including global interconnection signal carrying traces; a plurality of second conductive traces on the second metal layer, the second conductive traces being directly above the diffusion region and coupled to a power supply source and extending across the integrated circuit predominantly in a directions parallel to the rows; and a plurality of third conductive traces on the third metal layer, the third conductive traces extending across the integrated circuit predominantly in a direction parallel to the columns.

Claim 17

An integrated circuit architecture for a gate array, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of basic cells arranged as an array in rows and columns, each basic cell comprising: a diffusion region; and a gate region extending across the diffusion region in a vertical direction; a plurality of first conductive traces on a first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, the first conductive traces including global interconnection signal carrying traces; a plurality of second conductive traces on the second metal layer, the second conductive traces extending across the integrated circuit predominantly in a directions parallel to the rows; a plurality of third conductive traces on the third metal layer, the third conductive traces extending across the integrated circuit predominantly in a direction parallel to the columns; and substrate contacts interspersed throughout the gate array, wherein the second conductive traces are directly above the substrate contacts.

Claim 18

An integrated circuit architecture for a gate array, comprising: first, second, and third adjacent metal layers, wherein the first metal layer is disposed between the second metal layer and the basic cells, and the second metal layer is disposed between the third metal layer and the first metal layer; a plurality of basic cells arranged as an array in rows and columns, each basic cell comprising: a diffusion region; and a gate region extending across the diffusion region in a vertical direction; a plurality of first conductive traces on a first metal layer extending across the integrated circuit predominantly in a direction parallel to the rows, the first conductive traces including global interconnection signal carrying traces; a plurality of second conductive traces on the second metal layer, the second conductive traces extending across the integrated circuit predominantly in a directions parallel to the rows; a plurality of third conductive traces on the third metal layer, the third conductive traces extending across the integrated circuit predominantly in a direction parallel to the columns; and substrate contacts interspersed throughout the gate array, wherein the second conductive traces are directly above the substrate contacts.

Claim 19

A standard cell architecture comprising: a plurality of basic cells arranged in an array; first, second, and third adjacent metal layers, the second metal layer being above the first metal layer, and the third metal layer being above the second metal layer; a plurality of first conductive traces on the first metal layer for carrying local interconnection signals between basic cells to form macro cells; a plurality of second conductive traces on the first metal layer for carrying global interconnection signals to the basic cells, the second conductive traces predominantly extending across the basic cells in the direction parallel to the rows; a plurality of third conductive traces on the second metal layer for carrying global interconnection signals to the basic cells, the third conductive traces predominantly extending across the basic cells in a direction parallel to the rows; a plurality of fourth conductive traces on the second metal layer for carrying power to the basic cells, the fourth conductive traces predominantly extending across the basic cells in the direction parallel to the rows; and a plurality of fifth conductive traces on the third metal layer for carrying global interconnection signals to the basic cell, the fifth conductive traces predominantly extending across the basic cells in a direction parallel to the columns.

Claim 20

A standard cell architecture comprising: a plurality of basic cells arranged in an array; first, second, and third adjacent metal layers, the second metal layer being above the first metal layer, and the third metal layer being above the second metal layer; a plurality of first conductive traces on the first metal layer for carrying local interconnection signals between basic cells to form macro cells; a plurality of second conductive traces on the first metal layer for carrying global interconnection signals to the basic cells, the second conductive traces predominantly extending across the basic cells in the direction parallel to the rows; a plurality of third conductive traces on the second metal layer for carrying global interconnection signals to the basic cells, the third conductive traces predominantly extending across the basic cells in a direction parallel to the rows; a plurality of fourth conductive traces on the second metal layer for carrying power to the basic cells, the fourth conductive traces predominantly extending across the basic cells in the direction parallel to the rows; and a plurality of fifth conductive traces on the third metal layer for carrying global interconnection signals to the basic cell, the fifth conductive traces predominantly extending across the basic cells in a direction parallel to the columns.

Claim 21

The standard cell architecture of claim 13, further comprising a plurality of sixth conductive traces on the third metal layer for carrying power to the basic cells, the sixth conductive traces predominantly extending across the basic cells in the direction parallel to the columns.

Claim 22

In an integrated circuit implementing a standard cell architecture organized in perpendicular rows and columns of basic cells, a layout architecture, comprising: first, second, and third metal layers, the first metal layer being beneath the second metal layer, and the second metal layer being beneath the third metal layer, wherein no metal layer is disposed between the first and second metal layers, and no metal layer is disposed between the second and third metal layers; a plurality of first traces on the first metal layer extending across the integrated circuit in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces; and a plurality of third traces on the third metal layer extending across the gate array in a direction parallel to the columns.

Claim 23

In an integrated circuit implementing a standard cell architecture organized in perpendicular rows and columns of basic cells, a layout architecture, comprising: first, second, and third metal layers, the first metal layer being beneath the second metal layer, and the second metal layer being beneath the third metal layer, wherein no metal layer is disposed between the first and second metal layers, and no metal layer is disposed between the second and third metal layers; a plurality of first traces on the first metal layer extending across the integrated circuit in a direction parallel to the rows, wherein the first traces include global interconnection signal carrying traces; a plurality of second traces on the second metal layer extending across the integrated circuit in the direction parallel to the rows, wherein the second traces include global interconnection signal carrying traces; and a plurality of third traces on the third metal layer extending across the gate array in a direction parallel to the columns.

Claim 24

The integrated circuit of claim 15 further comprising a plurality of fourth traces on the first metal layer providing local interconnections for the basic cells.

Claim 25

The integrated circuit of claim 15 wherein the plurality of traces on the metal layer adjacent the metal layer closest to the basic cells comprises global interconnection signal carrying traces.

Claim 26

The integrated circuit of claim 17 wherein the global interconnection signal carrying traces are coupled to a power supply.

Claim 27

In an integrated circuit implementing a standard cell architecture organized in perpendicular rows and columns of basic cells, a layout architecture, comprising: a plurality of adjacent metal layers, each of said adjacent metal layers having a plurality of traces extending across the integrated circuit in a direction parallel to the rows; and a first metal layer adjacent to and above the first plurality of adjacent metal layer, the first metal layer having a plurality of traces extending across the gate array in a direction parallel to the columns.

Claim 28

In an integrated circuit implementing a standard cell architecture organized in perpendicular rows and columns of basic cells, a layout architecture, comprising: a plurality of adjacent metal layers, each of said adjacent metal layers having a plurality of traces extending across the integrated circuit in a direction parallel to the rows; and a first metal layer adjacent to and above the first plurality of adjacent metal layer, the first metal layer having a plurality of traces extending across the gate array in a direction parallel to the columns.

Claim 29

The layout architecture of claim 19 further comprising a first and second metal layer in the plurality of adjacent metal layers, the first metal layer being closest to the basic cells and the second metal layer being adjacent the first metal layer, wherein the plurality of traces in the second metal layer are coupled to a power supply for distributing power to the basic cells.