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US6087209A
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Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant
Assignee: Advanced Micro Devices Inc
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Filing: 1998-07-31
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Granted: 2000-07-11
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Expires: 2018-07-31
Abstract
Abstract Ultra shallow, low resistance LDD junctions are achieved by forming an LDD implant generating an interstitial-rich section and forming a sub-surface, non-amorphous region generating a vacancy-rich region substantially overlapping the interstitial rich region generated when forming the LDD implant. Embodiments include ion implanting, Ge or Si to form surface amorphous and sub-surface, non-amorphous regions, and implanting B or BF 2 to form the impurity region. Embodiments include forming the sub-surface, non-amorphous region before or after generating the surface amorphous region, and forming the impurity region before or after forming the sub-surface, non-amorphous region but after forming the surface amorphous region.
Inventors
- 👤 Geoffrey Choh-Fei Yeap
- 👤 Akif Sultan
- 👤 Shekhar Pramanick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10P; H10P30/00; H10P30/20; H10P30/21; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10P30/202; H10P30/204; H10P30/208; H10P30/225; H10P30/28; Y; Y10; Y10S; Y10S148/00; Y10S148/053
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
177 words
A method of manufacturing a semiconductor device, the method comprising: forming a surface amorphous region extending from and below a major surface of a semiconductor substrate, the amorphous region having a peak impurity concentration at a first depth from the major substrate surface; ion implanting a P-type impurity to form a dopant impurity region and generate an interstitial-rich region, a major portion of which is within the amorphous region, the dopant impurity region having a peak impurity concentration at a second depth from the major substrate surface; ion implanting to form a sub-surface, non-amorphous impurity region extending below, but not extending from, the major surface of the semiconductor substrate, and a vacancy-rich region substantially overlapping the interstitial-rich region generated when forming the dopant impurity region, wherein the non-amorphous impurity region has a peak impurity concentration at a third depth from the major substrate surface greater than the first and second depths; and activation annealing to form lightly doped source/drain regions extending below the major surface of the semiconductor surface and having a junction depth (X J ).
Claim 2
Independent Claim
177 words
A method of manufacturing a semiconductor device, the method comprising: forming a surface amorphous region extending from and below a major surface of a semiconductor substrate, the amorphous region having a peak impurity concentration at a first depth from the major substrate surface; ion implanting a P-type impurity to form a dopant impurity region and generate an interstitial-rich region, a major portion of which is within the amorphous region, the dopant impurity region having a peak impurity concentration at a second depth from the major substrate surface; ion implanting to form a sub-surface, non-amorphous impurity region extending below, but not extending from, the major surface of the semiconductor substrate, and a vacancy-rich region substantially overlapping the interstitial-rich region generated when forming the dopant impurity region, wherein the non-amorphous impurity region has a peak impurity concentration at a third depth from the major substrate surface greater than the first and second depths; and activation annealing to form lightly doped source/drain regions extending below the major surface of the semiconductor surface and having a junction depth (X J ).
Claim 3
Dependent Claim
21 words
The method according to claim 1, comprising ion implanting a Group IV element to form the amorphous and non-amorphous impurity regions.
Claim 4
Dependent Claim
28 words
The method according to claim 2, comprising ion implanting Si or Ge to form the amorphous region and implanting Si or Ge to form the non-amorphous impurity region.
Claim 5
Dependent Claim
30 words
The method according to claim 1, wherein: the amorphous region reduces channeling of the P-type impurities; and the sub-surface, non-amorphous impurity region reduces transient enhanced diffusion of the P-type impurities.
Claim 6
Dependent Claim
18 words
The method according to claim 4, wherein the X J is about 400 Å to about 700 Å.
Claim 7
Dependent Claim
41 words
The method according to claim 5, wherein: the first depth is about 50 Å to about 150 Å; the second depth is about 50 Å to about 200 Å; and the third depth is about 500 Å to about 900 Å.
Claim 8
Dependent Claim
139 words
The method according to claim 4, comprising: ion implanting Si or Ge at an energy of about 10 KeV to about 30 KeV at a dosage of about 1×10 15 to about 5×10 15 atoms/cm 2 to form the amorphous region; ion implanting B at an energy of about 0.5 KeV to about 2 KeV at a dosage of about 1×10 14 to about 2×10 15 atoms cm -2 or ion implanting BF 2 at an energy of 1 KeV to about 5 KeV at a dosage of about 1×10 14 to about 2×10 15 atoms/cm -2 , to form the impurity region; and ion implanting Si or Ge at an energy of about 40 KeV to about 80 KeV at a dosage of about 1×10 14 to about 8×10 14 atoms/cm 2 to form the non-amorphous impurity region.
Claim 9
Dependent Claim
139 words
The method according to claim 7, comprising: ion implanting Si or Ge at an energy of about 10 KeV to about 20 KeV at a dosage of about 1×10 15 to about 3×10 15 atoms/cm 2 to form the amorphous region; ion implanting B at an energy of about 0.5 KeV to about 1 KeV at a dosage of about 1×10 14 to about 9×10 14 atoms/cm 2 , or ion implanting BF 2 at an energy of about 1 KeV to about 3 KeV at a dosage of about 1×10 14 to about 9×10 14 atoms/cm 2 to form the impurity region; and ion implanting Si of Ge at an energy of about 50 KeV to about 70 KeV at a dosage of about 2×10 14 to about 5×10 14 atoms/cm 2 to form the non-amorphous impurity region.
Claim 10
Dependent Claim
21 words
The method according to claim 2, comprising, sequentially: forming the amorphous region; forming the impurity region; and forming the non-amorphous region.
Claim 11
Dependent Claim
22 words
The method according to claim 1, comprising, sequentially: forming the amorphous region; forming the non-amorphous impurity region; and forming the impurity region.
Claim 12
Dependent Claim
22 words
The method according to claim 1, comprising, sequentially: forming the non-amorphous region; forming the amorphous impurity region; and forming the impurity region.
Claim 13
Dependent Claim
20 words
The method according to claim 1, wherein the semiconductor device has a design rule of about 0.18 μm or under.
Claim 14
Dependent Claim
20 words
The method according to claim 1, comprising activation annealing at a temperature of about 500° C. to about 600° C.
Claim 15
Independent Claim
220 words
A method of manufacturing a semiconductor device, the method comprising: ion implanting Si or Ge to form a surface amorphous region extending from and below a major surface of a semiconductor substrate, the amorphous region having a peak impurity concentration at a first depth below the major substrate surface; ion implanting B or BF 2 to form a dopant impurity region a major portion of which is within the amorphous region, the dopant impurity region having a peak impurity concentration at a second depth below the major substrate surface and generating an interstitial-rich region; ion implanting Si or Ge to form a sub-surface, non-amorphous impurity region extending below, but not extending from, the major surface of a semiconductor substrate, wherein the non-amorphous impurity region has a peak impurity concentration at a third depth below the major substrate surface greater than the first and second depths and generate a vacancy-rich region substantially overlapping the interstitial-rich region generated when forming the impurity dopant region; and activation annealing to form lightly doped source/drain regions extending below the major surface of the semiconductor substrate and having a junction depth of about 400 Å to about 700 Å, wherein the amorphous region reduces channeling of B or BF 2 and the sub-surface, non-amorphous impurity region reduces transient enhanced diffusion of B or BF 2 .
Claim 16
Independent Claim
220 words
A method of manufacturing a semiconductor device, the method comprising: ion implanting Si or Ge to form a surface amorphous region extending from and below a major surface of a semiconductor substrate, the amorphous region having a peak impurity concentration at a first depth below the major substrate surface; ion implanting B or BF 2 to form a dopant impurity region a major portion of which is within the amorphous region, the dopant impurity region having a peak impurity concentration at a second depth below the major substrate surface and generating an interstitial-rich region; ion implanting Si or Ge to form a sub-surface, non-amorphous impurity region extending below, but not extending from, the major surface of a semiconductor substrate, wherein the non-amorphous impurity region has a peak impurity concentration at a third depth below the major substrate surface greater than the first and second depths and generate a vacancy-rich region substantially overlapping the interstitial-rich region generated when forming the impurity dopant region; and activation annealing to form lightly doped source/drain regions extending below the major surface of the semiconductor substrate and having a junction depth of about 400 Å to about 700 Å, wherein the amorphous region reduces channeling of B or BF 2 and the sub-surface, non-amorphous impurity region reduces transient enhanced diffusion of B or BF 2 .
Claim 17
Dependent Claim
20 words
The method according to claim 14, comprising activation annealing at a temperature of about 500° C. to about 600° C.
References Cited (Backward Citations)
WO1985000694A1
Cited
US4683645A
Cited
US4835112A
Cited
US5362670A
Cited
US5654210A
Cited
US5858864A
Cited
US5710055A
Cited
US5602045A
Cited
US5770485A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |