← Back to Patent Explorer
US5770485A Expired / Lapsed US ⏱️ 0.0 years remaining

MOSFET device with an amorphized source and fabrication method thereof

Assignee: Advanced Micro Devices Inc
•
Filing: 1997-03-04
•
Granted: 1998-06-23
•
Expires: 2017-03-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation in leakage current is obtained if the amorphized implant is performed on both the source and the drain sides of a transistor. However, since the source region is a low voltage region with a very shallow junction, MOSFETs in both n-channel and p-channel regions are formed with improved performance and reliability. A method of fabricating an integrated circuit includes forming a gate electrode over a semiconductor substrate, forming a source mask extending over the drain region of the semiconductor substrate, and implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate. The semiconductor substrate has a source region adjacent to a first side of the gate electrode and has a drain region adjacent to a second side of the gate electrode. The amorphous implant layer is self-aligned with the source mask and extends through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate. The method further includes the step of implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate. The source implant layer extends a shallower depth into the semiconductor substrate than the amorphous implant layer.

Inventors

  • 👤 Mark I. Gardner
  • 👤 H. Jim Fulford, Jr.
  • 👤 Derick J. Wristers

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 00:31
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/02; H10D84/03; H10D84/038; H10P30/208; H10P30/224; H10P30/225

Claims Analysis

Total Claims: 19
Claim 1
Independent Claim 157 words
A method of fabricating an integrated circuit comprising: forming a gate electrode over a semiconductor substrate, the semiconductor substrate having a source region adjacent to a first side of the gate electrode and having a drain region adjacent to a second side of the gate electrode; forming a source mask extending over the drain region of the semiconductor substrate; implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate, the amorphous implant layer being self-aligned with the source mask and extending through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate; and implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate, the source implant layer extending a shallower depth into the semiconductor substrate than the amorphous implant layer.
Claim 2
Independent Claim 157 words
A method of fabricating an integrated circuit comprising: forming a gate electrode over a semiconductor substrate, the semiconductor substrate having a source region adjacent to a first side of the gate electrode and having a drain region adjacent to a second side of the gate electrode; forming a source mask extending over the drain region of the semiconductor substrate; implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate, the amorphous implant layer being self-aligned with the source mask and extending through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate; and implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate, the source implant layer extending a shallower depth into the semiconductor substrate than the amorphous implant layer.
Claim 3
Dependent Claim 55 words
A method according to claim 1, wherein: forming the source mask further includes extending the source mask to partially cover the gate electrode, a portion of the gate electrode partially covered being a protected portion of the gate electrode and a portion of the gate electrode uncovered being an exposed portion of the gate electrode.
Claim 4
Dependent Claim 33 words
A method according to claim 1, wherein: implanting the amorphous implant layer includes implanting an implant species selected from the species including silicon (Si), argon (Ar), germanium (Ge), cobalt (Co) and carbon (C).
Claim 5
Dependent Claim 41 words
A method according to claim 1, wherein: implanting the amorphous implant layer includes implanting argon with a dosage in the range of 1×10 15 to 5×10 16 atoms/cm 2 and an energy in the range of 10 to 100 kiloelectron-volts (keV).
Claim 6
Dependent Claim 35 words
A method according to claim 1, further comprising: removing the source mask; and forming lightly-doped drain (LDD) regions in the semiconductor substrate, the LDD regions being implanted to a depth shallower than the source implant.
Claim 7
Dependent Claim 30 words
A method according to claim 5, further comprising: forming spacers on lateral edges of the gate electrodes; implanting the source/drain regions of the semiconductor substrate; and annealing the semiconductor substrate.
Claim 8
Dependent Claim 25 words
A method according to claim 1, further comprising: annealing the semiconductor substrate after implanting the amorphous implant layer and prior to implanting the source implant.
Claim 9
Dependent Claim 36 words
A method according to claim 1, further comprising: removing the exposed portion of the gate electrode previous to implanting the amorphous layer, the removed portion of the gate electrode exposing a region of the semiconductor substrate.
Claim 10
Dependent Claim 36 words
A method according to claim 1, further comprising: removing the exposed portion of the gate electrode subsequent to implanting the amorphous layer, the removed portion of the gate electrode exposing a region of the semiconductor substrate.
Claim 11
Independent Claim 219 words
A method of fabricating an integrated circuit comprising: forming a gate electrode over a semiconductor substrate, the semiconductor substrate having a source region adjacent to a first side of the gate electrode and having a drain region adjacent to a second side of the gate electrode; forming a source mask extending over the drain region of the semiconductor substrate and extending to partially cover the gate electrode, a portion of the gate electrode partially covered being a protected portion of the gate electrode and a portion of the gate electrode uncovered being an exposed portion of the gate electrode; removing the exposed portion of the gate electrode, the removed portion of the gate electrode exposing a region of the semiconductor substrate; implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate, the amorphous implant layer being self-aligned with the source mask and extending through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate; and implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate, the source implant layer extending a shallower depth into the semiconductor substrate than the amorphous implant layer.
Claim 12
Independent Claim 219 words
A method of fabricating an integrated circuit comprising: forming a gate electrode over a semiconductor substrate, the semiconductor substrate having a source region adjacent to a first side of the gate electrode and having a drain region adjacent to a second side of the gate electrode; forming a source mask extending over the drain region of the semiconductor substrate and extending to partially cover the gate electrode, a portion of the gate electrode partially covered being a protected portion of the gate electrode and a portion of the gate electrode uncovered being an exposed portion of the gate electrode; removing the exposed portion of the gate electrode, the removed portion of the gate electrode exposing a region of the semiconductor substrate; implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate, the amorphous implant layer being self-aligned with the source mask and extending through the exposed region of the semiconductor substrate and the source region of the semiconductor substrate; and implanting a source implant into the exposed region of the semiconductor substrate and the source region of the semiconductor substrate to form a source implant layer of the semiconductor substrate, the source implant layer extending a shallower depth into the semiconductor substrate than the amorphous implant layer.
Claim 13
Dependent Claim 21 words
A method according to claim 10, wherein: removing the exposed portion of the gate electrode precedes implanting the amorphous implant layer.
Claim 14
Dependent Claim 21 words
A method according to claim 10, wherein: implanting the amorphous implant layer precedes removing the exposed portion of the gate electrode.
Claim 15
Dependent Claim 33 words
A method according to claim 10, wherein: implanting the amorphous implant layer includes implanting an implant species selected from the species including silicon (Si), argon (Ar), germanium (Ge), cobalt (Co) and carbon (C).
Claim 16
Dependent Claim 41 words
A method according to claim 10, wherein: implanting the amorphous implant layer includes implanting argon with a dosage in the range of 1×10 15 to 5×10 16 atoms/cm 2 and an energy in the range of 10 to 100 kiloelectron-volts (keV).
Claim 17
Dependent Claim 35 words
A method according to claim 10, further comprising: removing the source mask; and forming lightly-doped drain (LDD) regions in the semiconductor substrate, the LDD regions being implanted to a depth shallower than the source implant.
Claim 18
Dependent Claim 30 words
A method according to claim 15, further comprising: forming spacers on lateral edges of the gate electrodes; implanting the source/drain regions of the semiconductor substrate; and annealing the semiconductor substrate.
Claim 19
Dependent Claim 25 words
A method according to claim 10, further comprising: annealing the semiconductor substrate after implanting the amorphous implant layer and prior to implanting the source implant.

References Cited (Backward Citations)

US5258319A Cited
US5547885A Cited
US5286664A Cited
US5420055A Cited
US5278082A Cited
US5338960A Cited
US5366915A Cited
US5578509A Cited
US5432106A Cited
US5633177A Cited
US5561072A Cited
US5360749A Cited
US5585286A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-06-22 2001-12-22 2002-06-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-06-22 2005-12-22 2006-06-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-06-22 2009-12-22 2010-06-23 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag