Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories

Claim 2

An interface apparatus, comprising: a multi-port memory having a plurality of data storage cells and having at least three independent bi-directional data ports that are configured to simultaneously and asynchronously write data to and read data from the plurality of data storage cells without allocation of access between the data ports and the plurality of data storage cells; first means for coupling a first port of the bi-directional data ports to a first bi-directional data bus; second means for coupling a second port of the bi-directional data ports to a second bi-directional data bus; and a processor coupled to a third port of the bi-directional data ports for operating on data in the plurality of data storage cells.

Claim 3

An interface apparatus as defined in claim 1, wherein: the first data bus uses a n-data bits; the second data bus uses a m data bits where m is greater than n; and the multi-port memory is a triple-port memory that uses a quad-port memory having one of its four ports configured for the first data bus and having two of its four ports configured for the second bus data bus for supporting the wider m-bits data address.

Claim 4

An interface apparatus as defined in claim 1, wherein: the first coupling means includes a first data bus interface unit coupled between the first bi-directional data bus and the first bi-directional data port for asynchronously writing data to and reading data from the plurality of data storage cells; the second coupling means includes a second data bus interface unit coupled between the second bi-directional data bus and the second bi-directional data port for asynchronously writing data to and reading data from the plurality of data storage cells; and the processor asynchronously operates on data previously written by one of the first and second data bus interfaces in a one portion of the plurality of data storage cells while the first and second bus interfaces simultaneously write data to and read data from other portions, respectively, of the plurality of data storage cells.

Claim 5

An interface apparatus as defined in claim 3, further comprising a pass-through logic unit coupled between the first and second bus interface units for providing a data bridge between the first and second data buses.

Claim 6

An interface apparatus as defined in claim 4, wherein the data bridge performs a protocol conversion between a split transaction protocol and an unified transaction protocol.

Claim 7

An interface apparatus as defined in claim 4, wherein: the first data bus is a PCI data bus; the first data bus interface unit is a PCI interface unit; the second data bus is an SCI data bus; the second data bus interface is an SCI interface unit; and the pass-through logic unit translates a data address on the SCI data bus to a data address on the PCI data bus for providing an SCI-to-PCI data bus bridge.

Claim 8

An interface apparatus as defined in claim 6, wherein the pass-through logic translates a data address on the PCI data bus to a data address on the SCI data bus for providing a PCI-to-SCI data bus bridge.

Claim 9

An interface apparatus as defined in claim 4, wherein: the SCI data bus uses a 64-bit data address; the PCI data bus uses a 32-bit data address; and the multi-port memory is a triple-port memory that uses a quad-port memory having one of its four ports configured for the PCI data bus and having two of its four ports configured for the SCI bus data bus for supporting the wider 64-bit data address.

Claim 10

An interface apparatus as defined in claim 8, wherein the pass-through logic unit implements a fly-by address translation between the SCI bus interface unit and the PCI bus interface unit.

Claim 11

An interface apparatus as defined in claim 3, wherein: the first data bus is a host PCI data bus; the first data bus interface unit is a first DMA interface unit; the second data bus is a slave PCI data bus; the second data bus interface unit is a second DMA interface unit; and the pass-through logic unit forwards a data address on the host PCI data bus to the slave PCI data bus and forwards a data address on the slave PCI data bus to the host PCI data bus to provide a PCI-to-PCI bridge unit.

Claim 12

An interface apparatus as defined in claim 3, wherein the processor schedules block reads between the first and second data bus interface units to implement a chain-mode DMA data transfer.

Claim 13

An interface apparatus as defined in claim 3, further comprising an internal bus that is coupled to the processor, to the first data bus interface unit, and to the second data bus interface unit for enabling communication of control and configuration instructions among the processor and the first and second data bus interface units.

Claim 14

An interface apparatus as defined in claim 1, further comprising third means for coupling a fourth port of the bi-directional data ports to a third bi-directional data bus.

Claim 15

An interface apparatus as defined in claim 13, wherein: the third coupling means includes a third bi-directional data bus interface unit coupled to a fourth port of the bi-directional data ports; and the interface apparatus further comprises a pass-through logic unit coupled between the first and second bus interface units for providing a local network bridge between the first and second data buses.

Claim 16

An interface apparatus as defined in claim 14, wherein: the first data bus is a first Ethernet data bus; the first coupling means includes a first Ethernet interface unit; the second data bus is a second Ethernet data bus; the second coupling means includes a second Ethernet interface unit; the third coupling means includes an ATM interface unit coupled between the third bi-directional data bus and the fourth bi-directional data port; and the pass-through logic unit provides a data bridge between the first and second Ethernet data buses.

Claim 17

An interface apparatus as defined in claim 1, wherein the processor includes means for performing encryption and decryption on data stored in the multi-port memory.

Claim 18

An interface apparatus as defined in claim 1, further comprising a second processor coupled to a fourth port of the bi-directional data ports for operating on data in the plurality of data storage cells.

Claim 19

An interface apparatus as defined in claim 1, wherein the processor is a digital state machine.

Claim 20

An interface apparatus as defined in claim 1, wherein the processor includes local memory for implementing a reflective memory protocol.

Claim 21

An interface apparatus as defined in claim 1, wherein the processor includes local memory for implementing a memory cache.

Claim 22

An interface apparatus, comprising: a processor; a first bus interface for receiving data from and transmitting data to a first data bus; a second bus interface for receiving data from and transmitting data to a second data bus; a triple port memory having first, second, and third ports for storing data into a plurality of storage cells and for reading stored data from the storage cells without allocation of access between the ports and the plurality of data storage cells; the first port being coupled to the first bus interface such that data received from the first data bus is stored in the storage cells and data read from the storage cells by the first bus interface is transmitted to the first data bus; the second port being coupled to the second bus interface such that data received from the second data bus is stored in the storage cells and data read from the storage cells by the second bus interface is transmitted to the second data bus; the processor being coupled to the third port for reading, processing, and storing data in the storage cells; and wherein the data stored to a particular storage cell through a particular port is available to be asynchronously read by another port independently of the particular port while the particular port is reading data from or storing data to another storage cell.

Claim 23

An interface apparatus, comprising: a processor; a first bus interface for receiving data from and transmitting data to a first data bus; a second bus interface for receiving data from and transmitting data to a second data bus; a triple port memory having first, second, and third ports for storing data into a plurality of storage cells and for reading stored data from the storage cells without allocation of access between the ports and the plurality of data storage cells; the first port being coupled to the first bus interface such that data received from the first data bus is stored in the storage cells and data read from the storage cells by the first bus interface is transmitted to the first data bus; the second port being coupled to the second bus interface such that data received from the second data bus is stored in the storage cells and data read from the storage cells by the second bus interface is transmitted to the second data bus; the processor being coupled to the third port for reading, processing, and storing data in the storage cells; and wherein the data stored to a particular storage cell through a particular port is available to be asynchronously read by another port independently of the particular port while the particular port is reading data from or storing data to another storage cell.

Claim 24

An interface apparatus, comprising: a multi-port memory having a at least four independent bi-directional data ports; a plurality of bus interfaces, each interface being connected to one of a separate data port of the at least four independent data ports for storing data in and reading data from the multi-port memory; and a plurality of data processors, each data processor being connected to a separate data port of the at least four independent data ports for simultaneously reading data from different portions of the multi-port memory, processing the stored data, and storing the processed data in the multi-port memory without allocation of access by the at least four independent data ports to the multi-port memory during reading data from and storing data to the multi-port memory.

Claim 25

An interface apparatus, comprising: a multi-port memory having a at least four independent bi-directional data ports; a plurality of bus interfaces, each interface being connected to one of a separate data port of the at least four independent data ports for storing data in and reading data from the multi-port memory; and a plurality of data processors, each data processor being connected to a separate data port of the at least four independent data ports for simultaneously reading data from different portions of the multi-port memory, processing the stored data, and storing the processed data in the multi-port memory without allocation of access by the at least four independent data ports to the multi-port memory during reading data from and storing data to the multi-port memory.

Claim 26

An interface apparatus as defined in claim 22, wherein each of the plurality of processors includes means for performing encryption and decryption on data stored in the multi-port memory.

Claim 27

An interface apparatus as defined in claim 22, further comprising an internal bus connected between the plurality of bus interfaces and the plurality of data processors for communicating control and configuration instructions between the plurality of data processors and the plurality of bus interfaces.

Claim 28

An interface apparatus as defined in claim 22, further comprising a pass-through logic device for transmitting data between two bus interfaces using the multi-port memory independent of the processor.

Claim 29

An interface apparatus as defined in claim 25, wherein the pass-through logic device implements a fly-by address translation between the two bus interfaces.

Claim 30

An interface apparatus as defined in claim 22, wherein the multi-port memory is a quad-port memory implementing a triple-port memory with different port data bus widths using a quad-port memory.

Claim 33

An interface apparatus for interfacing data as defined in claim 3, wherein processed data stored in a portion of the plurality of data storage cells is read through a third data port while data stored in a second portion of the plurality of data storage cells is independently and simultaneously processed though the second port and while data is independently and simultaneously received through the first port from the first data bus and stored into a third portion of the plurality of storage cells.

Claim 34

An interface apparatus, comprising: a multi-port memory having a plurality of data storage cells and having at least three independent bi-directional data ports that are configured to simultaneously and independently write data to and read data from the plurality of data storage cells without allocation of access between the data ports and the plurality of data storage cells; first means for coupling a first port of the bi-directional data ports to a first bi-directional data bus; second means for coupling a second port of the bi-directional data ports to a second bi-directional data bus; and a processor coupled to a third port of the bi-directional data ports for operating on data in the plurality of data storage cells.

Claim 35

An interface apparatus, comprising: a multi-port memory having a plurality of data storage cells and having at least three independent bi-directional data ports that are configured to simultaneously and independently write data to and read data from the plurality of data storage cells without allocation of access between the data ports and the plurality of data storage cells; first means for coupling a first port of the bi-directional data ports to a first bi-directional data bus; second means for coupling a second port of the bi-directional data ports to a second bi-directional data bus; and a processor coupled to a third port of the bi-directional data ports for operating on data in the plurality of data storage cells.